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a preliminary technical data tigersharc and the tigersharc logo are registered trademar ks of analog devices, inc. blackfin ? embedded processor adsp-bf534 rev. pre information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without no tice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o.box 9106, norwood, ma 02062-9106 u.s.a. tel:781/329-4700 www.analog.com fax:781/461-3113 ? 2005 analog devices, inc. all rights reserved. features up to 500 mhz high-performance blackfin processor two 16-bit macs, two 40-bit alus, four 8-bit video alus, 40-bit shifter risc-like register and instruction model for ease of programming and compiler-friendly support advanced debug, trace, an d performance-monitoring 0.8v to 1.2v core v dd with on-chip voltage regulation 2.5 v and 3.3 v-tolerant i/o with specific 5 v-tolerant pins 182-ball mbga and 208-ball sparse mbga packages lead bearing and lead free package choices memory 132k bytes of on-chip memory: 16k bytes of instruction sram/cache 48k bytes of instruction sram 32k bytes of data sram/cache 32k bytes of data sram 4k bytes of scratchpad sram external memory controller with glueless support for sdram and asynchronous 8/16-bit memories flexible booting options from external flash, spi and twi memory or from spi, twi, and uart host devices two dual-channel memory dma controllers memory management unit pr oviding memory protection peripherals controller area network (can) 2.0b interface parallel peripheral interface (ppi), supporting itu-r 656 video data formats two dual-channel, full-duplex synchronous serial ports (sports), supporting eight stereo i 2 s channels 12 peripheral dmas two memory-to-memory dmas wi th external request lines event handler with 32 interrupt inputs serial peripheral interface (spi)-compatible two uarts with irda? support two-wire interface (twi) controller eight 32-bit timer/counters with pwm support real-time clock (rtc) and watchdog timer 32-bit core timer 48 general-purpose i/os (gpios), 8 with high current drivers on-chip pll capable of 1x to 63x frequency multiplication debug/jtag interface figure 1. function al block diagram voltage regulator dma controller event controller/ core timer rtc uart 0-1 timers 0-7 ppi sport1 spi external port flash, sdram control boot rom jtag test and emulation watchdog timer l1 instruction memory l1 data memory mmu b core / system bus interface twi can sport0 gpio port f gpio port g gpio port h port j
rev. pre | page 2 of 60 | july 2005 adsp-bf534 preliminary technical data table of contents general description ................................................. 3 portable low-power architecture ............................. 3 system integration ................................................ 3 adsp-bf534 processor peripherals ... ........................ 3 blackfin processor core .......................................... 4 memory architecture ............................................ 4 internal (on-chip) memory ................................. 4 external (off-chip) memory ................................ 5 i/o memory space ............................................. 5 booting ........................................................... 5 event handling ................................................. 6 core event controller (cec) ................................ 6 system interrupt controller (sic) .......................... 6 event control ................................................... 7 dma controllers .................................................. 8 real-time clock (rtc) .......................................... 8 watchdog timer .................................................. 9 timers ............................................................... 9 serial ports (sports) ............................................ 9 serial peripheral interface (spi) port ....................... 10 uart ports (uarts) .......................................... 10 controller area network (can) ............................ 10 twi controller interface ...................................... 11 ports ................................................................ 11 general-purpose i/o (gpio) .............................. 11 parallel peripheral interface (ppi) ........................... 11 dynamic power management ................................ 12 full-on operating mode C maximum performance . 12 active operating mode C moderate power savings .. 12 sleep operating mode C high dynamic power savings .............................................. 12 deep sleep operating mode C maximum dynamic power savings .............................................. 12 hibernate operating mode C maximum static power savings ....................................................... 12 power savings ................................................. 12 voltage regulation .............................................. 13 clock signals ..................................................... 13 booting modes ................................................... 15 instruction set description ................................... 15 development tools ............................................. 16 ez-kit lite evaluation board ............................ 16 designing an emulator -compatible processor board (target) ................................................. 16 related documents .............................................. 16 pin descriptions .................................................... 17 specifications ........................................................ 20 recommended operating conditions ...................... 20 absolute maximum ratings ................................... 22 esd sensitivity ................................................... 22 timing specifications ........................................... 23 asynchronous memory read cycle timing ............ 25 asynchronous memory write cycle timing ........... 26 sdram interface timing .................................. 27 external port bus request and grant cycle timing .. 28 external dma request timing ............................ 29 parallel peripheral interface timing ...................... 30 serial ports ..................................................... 31 serial peripheral interface (spi) portmaster timing ........................................................36 serial peripheral interface (spi) portslave timing . 37 universal asynchronous receiver-transmitter (uart) portsreceive and transmit timing ..... 38 general-purpose port timing ............................. 39 timer cycle timing .......................................... 40 jtag test and emulation port timing ................. 41 twi controller timing ..................................... 42 output drive currents ......................................... 46 power dissipation ............................................... 49 test conditions .................................................. 49 output enable time ......................................... 49 output disable time ......................................... 50 example system hold time calculation ................ 50 environmental conditions .................................... 51 182-ball mini-bga pinout ....................................... 52 208-ball sparse mi ni-bga pinout .............................. 55 outline dimensions ................................................ 58 ordering guide ..................................................... 59
adsp-bf534 preliminary technical data rev. pre | page 3 of 60 | july 2005 revision history revision pre: corrections to prd because of changes to order- ing guide, changes to recommended operating conditions, other minor corrections. changes to: figure 2 ................................................................. 5 dynamic power management .................................... 12 clock signals ......................................................... 13 figure 6 ................................................................ 14 booting modes ....................................................... 15 development tools ................................................. 16 related documents ................................................. 16 recommended operating conditions ......................... 20 figure 8 ............................................................... 22 tables 10 and 11 .................................................... 23 figures 42 and 43 ....................................................54 table 44 ................................................................55 table 45 ................................................................56 figures 44 and 45 ....................................................57 figures 46 and 47 ....................................................58 ordering guide ..................................................... 59 general description the adsp-bf534 processor is a me mber of the blackfin family of products, incorporating the analog devices/intel micro sig- nal architecture (msa). blackfin processors combine a dual- mac state-of-the-art signal proc essing engine, the advantages of a clean, orthogonal risc-lik e microprocessor instruction set, and single-instruction, multiple -data (simd) multimedia capa- bilities into a single in struction-set architecture. specific performance and memory configuration is shown in table 1 . by integrating a rich set of indu stry-leading system peripherals and memory, blackfin processors are the platform of choice for next-generation applications that require risc-like program- mability, multimedia support and leading- edge signal processing in one integrated package. portable low-power architecture blackfin processors provide world-class power management and performance. blackfin processors are designed in a low power and low voltage design methodology and feature on-chip dynamic power management, the ability to vary both the volt- age and frequency of operation to significantly lower overall power consumption. varying the voltage and frequency can result in a substantial reduction in power consumption, com- pared with just varying the frequency of operation. this translates into longer battery life for portable appliances. system integration the adsp-bf534 processor is a hi ghly integrated system-on-a- chip solutions for the next generation of embedded network connected applications. by combining industry-standard inter- faces with a high performance si gnal processing core, users can develop cost-effective solutions quickly without the need for costly external components. th e system peripherals include a can 2.0b controller, a twi contro ller, two uart ports, an spi port, two serial ports (sports) , nine general purpose 32-bit timers (eight with pwm capability), a real-time clock, a watch- dog timer, and a parallel peripheral interface. adsp-bf534 processor peripherals the adsp-bf534 processo r contains a rich set of peripherals connected to the core via severa l high bandwidth buses, provid- ing flexibility in system configuration as well as excellent overall system performance (see the block diagram on page 1 ). the general-purpose peripherals incl ude functions such as uarts, spi, twi, timers with pwm (pulse width modulation) and pulse measurement capability, general purpose i/o pins, a real- time clock, and a watchdog time r. this set of functions satis- fies a wide variety of typica l system support needs and is augmented by the system expansio n capabilities of the part. the adsp-bf534 processor contains dedicated network communi- cation modules and high-speed serial and parallel ports, an interrupt controller for flexible management of interrupts from the on-chip peripherals or extern al sources, and power manage- ment control functions to tailor the performance and power characteristics of the processor and system to many application scenarios. all of the peripherals, except for general-purpose i/o, can, twi, real-time clock, and timers, are supported by a flexible dma structure. there are also separate memory dma channels dedicated to data transfers be tween the processor's various memory spaces, including external sdram and asynchronous memory. multiple on-chip buse s running at up to 133 mhz provide enough bandwidth to keep the processor core running along with activity on all of the on-chip and external peripherals. table 1. processor comparison adsp-bf534 maximum performance 500 mhz instruction sram/cache 16k bytes instruction sram 48k bytes data sram/cache 32k bytes data sram 32k bytes scratchpad 4k bytes
rev. pre | page 4 of 60 | july 2005 adsp-bf534 preliminary technical data the adsp-bf534 processor includes an on-chip voltage regula- tor in support of the adsp-b f534 processor dynamic power management capability. the volt age regulator provides a range of core voltage levels when su pplied from a single 2.25 v to 3.6 v input. the voltage regulator can be bypassed at the user's discretion. blackfin processor core as shown in figure 2 on page 5 , the blackfin processor core contains two 16-bit mu ltipliers, two 40-bit accumulators, two 40-bit alus, four video alus, an d a 40-bit shifter. the compu- tation units process 8-bit, 16-bit, or 32-bit data from the register file. the compute register file contains eight 32-bit registers. when performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. all operands for compute operations come from the multiported register file and instruction constant fields. each mac can perform a 16-bit by 16-bit multiply in each cycle, accumulating the results into the 40-bit accumulators. signed and unsigned formats, rounding, and saturation are supported. the alus perform a traditional set of arithmetic and logical operations on 16-bit or 32-bit data. in addition, many special instructions are included to acce lerate various signal processing tasks. these include bit operations such as field extract and pop- ulation count, modulo 2 32 multiply, divide primitives, saturation and rounding, and sign/exponent detection. the set of video instructions include byte alignment and packing operations, 16- bit and 8-bit adds with clipping, 8-bit average operations, and 8- bit subtract/absolute value/accu mulate (saa) operations. also provided are the compare/select and vector search instructions. for certain instructions, two 16- bit alu operations can be per- formed simultaneously on register pairs (a 16-bit high half and 16-bit low half of a co mpute register). by al so using the second alu, quad 16-bit operations are possible. the 40-bit shifter can perform shifts and rotates and is used to support normalization, field extract, and field deposit instructions. the program sequencer controls the flow of instruction execu- tion, including instruction alignment and decoding. for program flow control, the sequ encer supports pc relative and indirect conditional jumps (with static branch prediction), and subroutine calls. hardware is provided to support zero-over- head looping. the architecture is fully interlocked, meaning that the programmer need not manage the pipeline when executing instructions with data dependencies. the address arithmetic unit prov ides two addresses for simulta- neous dual fetches from memory. it contains a multiported register file consisti ng of four sets of 32-bit index, modify, length, and base registers (for circular buffering), and eight additional 32-bit pointer regist ers (for c-style indexed stack manipulation). blackfin processors support a modified harvard architecture in combination with a hierarchical memory structure. level 1 (l1) memories are those that typically operate at the full processor speed with little or no latency. at the l1 level, the instruction memory holds instructions only. the two data memories hold data, and a dedicated scratchpad data memory stores stack and local variable information. in addition, multiple l1 memory blocks are provided, offering a configurable mix of sram an d cache. the memory manage- ment unit (mmu) provides memory protection for individual tasks that may be oper ating on the core and can protect system registers from unintended access. the architecture provides three modes of operation: user mode, supervisor mode, and emulation mode. user mode has restricted access to certain syst em resources, thus providing a protected software environment, while supervisor mode has unrestricted access to the system and core resources. the blackfin processor instruct ion set has been optimized so that 16-bit opcodes represent the most frequently used instruc- tions, resulting in excellent co mpiled code density. complex dsp instructions are encoded into 32-bit opcodes, representing fully featured multifunction inst ructions. blackfin processors support a limited multi-issue ca pability, where a 32-bit instruc- tion can be issued in parallel with two 16-bit instructions, allowing the programmer to use ma ny of the core resources in a single instruction cycle. the blackfin processor assembly language uses an algebraic syn- tax for ease of coding and readability. the architecture has been optimized for use in conjunction with the c/c++ compiler, resulting in fast and effici ent software implementations. memory architecture the adsp-bf534 processor views memory as a single unified 4g byte address space, using 32- bit addresses. all resources, including internal memory, external memory, and i/o control registers, occupy separate sect ions of this common address space. the memory portions of this address space are arranged in a hierarchical structure to provide a good cost/performance balance of some very fast, low- latency on-chip memory as cache or sram, and larger, lower-cost and performance off-chip memory systems. see figure 3 on page 6 . the on-chip l1 memory system is the highest-performance memory available to the blackfin processor. the off-chip mem- ory system, accessed through the external bus interface unit (ebiu), provides expansion wi th sdram, flash memory, and sram, optionally accessing up to 516m bytes of physical memory. the memory dma controller prov ides high-bandwidth data- movement capability. it can perf orm block transfers of code or data between the internal memo ry and the external memory spaces. internal (on-chip) memory the adsp-bf534 processor has th ree blocks of on-chip mem- ory providing high-bandwidth access to the core.
adsp-bf534 preliminary technical data rev. pre | page 5 of 60 | july 2005 the first block is the l1 instruction memory, consisting of 64k bytes sram, of which 16k bytes can be configured as a four-way set-asso ciative cache. this memory is accessed at full processor speed. the second on-chip memory block is the l1 data memory, con- sisting of two banks of 32k byte s each. each memory bank is configurable, offering both cache and sram functionality. this memory block is accessed at full processor speed. the third memory block is a 4k byte scratchpad sram which runs at the same speed as the l1 memories, but is only accessible as data sram and cannot be configured as cache memory. external (off-chip) memory external memory is accessed via the ebiu. this 16-bit interface provides a glueless connection to a bank of synchronous dram (sdram) as well as up to four banks of asynchronous memory devices including flash, epro m, rom, sram, and memory mapped i/o devices. the pc133-compliant sdram cont roller can be programmed to interface to up to 512m bytes of sdram. a separate row can be open for each sdram internal bank and the sdram con- troller supports up to 4 internal sdram banks, improving overall performance. the asynchronous memory cont roller can be programmed to control up to four banks of devi ces with very flexible timing parameters for a wide variety of devices. each bank occupies a 1m byte segment regardless of the size of the devices used, so that these banks will only be cont iguous if each is fully popu- lated with 1m byte of memory. i/o memory space the adsp-bf534 processor does not define a separate i/o space. all resources are mapped through the flat 32-bit address space. on-chip i/o devices have their control registers mapped into memory-mapped registers ( mmrs) at addresses near the top of the 4g byte address space. these are separated into two smaller blocks, one which cont ains the control mmrs for all core functions, and the other which contains the registers needed for setup and control of the on-chip peripherals outside of the core. the mmrs are accessi ble only in supervisor mode and appear as reserved space to on-chip peripherals. booting the adsp-bf534 processor contai ns a small on-chip boot ker- nel, which configures the appropri ate peripheral for booting. if the adsp-bf534 processor is conf igured to boot from boot figure 2. blackfin processor core sequencer align decode loop buffer 16 16 8 888 40 40 a0 a1 barrel shifter data arithmetic unit control unit r7.h r6.h r5.h r4.h r3.h r2.h r1.h r0.h r7.l r6.l r5.l r4.l r3.l r2.l r1.h r0.l astat 40 40 32 32 32 32 32 32 32 ld0 ld1 sd dag0 dag1 address arithmetic unit i3 i2 i1 i0 l3 l2 l1 l0 b3 b2 b1 b0 m3 m2 m1 m0 sp fp p5 p4 p3 p2 p1 p0 da1 da0 32 32 32 preg rab 32 to memory
rev. pre | page 6 of 60 | july 2005 adsp-bf534 preliminary technical data rom memory space, the processo r starts executing from the on-chip boot rom. for more information, see booting modes on page 15 . event handling the event controller on the adsp -bf534 processor handles all asynchronous and synchronous ev ents to the processor. the adsp-bf534 processor provides event handling that supports both nesting and prioritization. nesting allows multiple event service routines to be active simultaneously. prioritization ensures that servicing of a hi gher-priority event takes prece- dence over servicing of a lower- priority event. the controller provides support for five different types of events: ? emulation C an emulation ev ent causes the processor to enter emulation mode, allowing command and control of the processor via the jtag interface. ? reset C this event resets the processor. ? non-maskable interrupt (nmi) C the nmi event can be generated by the software watchdog timer or by the nmi input signal to the processor. the nmi event is frequently used as a power-down indicator to initiate an orderly shut- down of the system. ? exceptions C events that occur synchronously to program flow (i.e., the exception will be taken before the instruction is allowed to complete). condit ions such as data alignment violations and undefined instructions cause exceptions. ? interrupts C events that occur asynchronously to program flow. they are caused by input pins, timers, and other peripherals, as well as by an explicit software instruction. each event type has an associated register to hold the return address and an associated return -from-event inst ruction. when an event is triggered, the state of the processor is saved on the supervisor stack. the adsp-bf534 processor event controller consists of two stages, the core event controlle r (cec) and the system inter- rupt controller (sic). the core event controller works with the system interrupt controller to prioritize and control all sys- tem events. conceptually, interrup ts from the peripherals enter into the sic, and are then routed directly into the general-pur- pose interrupts of the cec. core event controller (cec) the cec supports nine general-purpose interrupts (ivg15C7), in addition to the dedicated interrupt and exception events. of these general-purpose interrupts, the two lowest-priority inter- rupts (ivg15C14) are recommended to be reserved for software interrupt handlers, leaving seven prioritized interrupt inputs to support the peripherals of the adsp-bf534 processor. table 2 describes the inputs to the cec, identifies their names in the event vector table (evt), and lists their priorities. system interrupt controller (sic) the system interrupt controller provides the mapping and routing of events from the many peripheral interrupt sources to the prioritized general-purpose interrupt inputs of the cec. figure 3. adsp-bf534 inte rnal/external memory map reserved core mmr registers (2m byte) reserved scratchpad sram (4k byte) instruction bank b sram (16k byte) system mmr registers (2m byte) reserved reserved data bank b sram / cache (16k byte) data bank b sram (16k byte) data bank a sram / cache (16k byte) async memory bank 3 (1m byte) async memory bank 2 (1m byte) async memory bank 1 (1m byte) async memory bank 0 (1m byte) sdram memory (16m byte - 512m byte) instruction sram / cache (16k byte) i n t e r n a l m e m o r y m a p e x t e r n a l m e m o r y m a p 0xffff ffff 0xffe0 0000 0xffb0 0000 0xffa1 4000 0xffa1 0000 0xff90 8000 0xff90 4000 0xff80 8000 0xff80 4000 0x2040 0000 0x2030 0000 0x2020 0000 0x2010 0000 0x2000 0000 0xef00 0000 0x0000 0000 0xffc0 0000 0xffb0 1000 0xffa0 0000 data bank a sram (16k byte) 0xff90 0000 0xff80 0000 reserved reserved 0xffa0 c000 0xffa0 8000 instruction bank a sram (32k byte) reserved boot rom (2k byte) 0xef00 0800 table 2. core event controller (cec) priority (0 is highest) event class evt entry 0emulation/test controlemu 1 reset rst 2 non-maskable interrupt nmi 3exceptionevx 4 reserved 5 hardware error ivhw 6 core timer ivtmr 7 general interrupt 7 ivg7 8 general interrupt 8 ivg8 9 general interrupt 9 ivg9 10 general interrupt 10 ivg10 11 general interrupt 11 ivg11 12 general interrupt 12 ivg12 13 general interrupt 13 ivg13 14 general interrupt 14 ivg14 15 general interrupt 15 ivg15
adsp-bf534 preliminary technical data rev. pre | page 7 of 60 | july 2005 although the adsp-bf534 proce ssor provides a default map- ping, the user can alter the mappin gs and priorities of interrupt events by writing the appropri ate values into the interrupt assignment registers (iar). table 3 describes the inputs into the sic and the default mappings into the cec. event control the adsp-bf534 processor provides the user with a very flexi- ble mechanism to control the processing of events. in the cec, three registers are used to coordinate and control events. each register is 16 bits wide: ? cec interrupt latch register (ilat) C the ilat register indicates when events have been latched. the appropriate bit is set when the processo r has latched the event and cleared when the even t has been accepted into the system. this register is updated automatically by the controller, but it may be written only when its corresponding imask bit is cleared. ? cec interrupt mask regist er (imask) C the imask reg- ister controls the masking and unmasking of individual events. when a bit is set in the imask register, that event is unmasked and will be processe d by the cec when asserted. a cleared bit in the imask re gister masks the event, pre- venting the processor from servicing the event even though the event may be latched in the ilat register. this register may be read or written while in supervisor mode. (note that general-purpose interrupts can be globally enabled and disabled with the sti and cl i instructions, respectively.) ? cec interrupt pending register (ipend) C the ipend register keeps track of all ne sted events. a set bit in the ipend register indicates the event is currently active or nested at some level. this re gister is updated automatically by the controller but may be read while in supervisor mode. table 3. system interrupt controller (sic) peripheral interrupt event default mapping peripheral interrupt id pll wakeup ivg7 0 dma error (generic) ivg7 1 dmar0 block interrupt ivg7 1 dmar1 block interrupt ivg7 1 dmar0 overflow error ivg7 1 dmar1 overflow error ivg7 1 can error ivg7 2 sport 0 error ivg7 2 sport 1 error ivg7 2 ppi error ivg7 2 spi error ivg7 2 uart0 error ivg7 2 uart1 error ivg7 2 real-time clock ivg8 3 dma channel 0 (ppi) ivg8 4 dma channel 3 (sport 0 rx) ivg9 5 dma channel 4 (sport 0 tx) ivg9 6 dma channel 5 (sport 1 rx) ivg9 7 dma channel 6 (sport 1 tx) ivg9 8 twi ivg10 9 dma channel 7 (spi) ivg10 10 dma channel 8 (uart0 rx) ivg10 11 dma channel 9 (uart0 tx) ivg10 12 dma channel 10 (uart1 rx) ivg10 13 dma channel 11 (uart1 tx) ivg10 14 can rx ivg11 15 can tx ivg11 16 dma channel 1 ivg11 17 port h interrupt a ivg11 17 dma channel 2 ivg11 18 port h interrupt b ivg11 18 timer 0 ivg12 19 timer 1 ivg12 20 timer 2 ivg12 21 timer 3 ivg12 22 timer 4 ivg12 23 timer 5 ivg12 24 timer 6 ivg12 25 timer 7 ivg12 26 port f, g interrupt a ivg12 27 port g interrupt b ivg12 28 dma channels 12 and 13 (memory dma stream 0) ivg13 29 dma channels 14 and 15 (memory dma stream 1) ivg13 30 software watchdog timer ivg13 31 port f interrupt b ivg13 31 table 3. system interrupt co ntroller (sic) (continued) peripheral interrupt event default mapping peripheral interrupt id
rev. pre | page 8 of 60 | july 2005 adsp-bf534 preliminary technical data the sic allows further control of event processing by providing three 32-bit interrupt control and status registers. each register contains a bit corresponding to each of the peripheral interrupt events shown in table 3 on page 7 . ? sic interrupt mask register (sic_imask)C this register controls the masking and unma sking of each peripheral interrupt event. when a bit is set in the register, that peripheral event is unmasked and will be processed by the system when asserted. a cleared bit in the register masks the peripheral event, preventi ng the processor from servic- ing the event. ? sic interrupt status regist er (sic_isr) C as multiple peripherals can be ma pped to a single event, this register allows the software to dete rmine which peripheral event source triggered the interrupt. a set bit indicates the peripheral is asserting the interrupt, and a cleared bit indi- cates the peripheral is not asserting the event. ? sic interrupt wakeup enable register (sic_iwr) C by enabling the correspo nding bit in this register, a peripheral can be configured to wake up the processor, should the core be idled when the event is generated. ( for more infor- mation, see dynamic power management on page 12. ) because multiple interrupt source s can map to a single general- purpose interrupt, multiple puls e assertions can occur simulta- neously, before or during interr upt processing for an interrupt event already detected on this interrupt input. the ipend reg- ister contents are monitored by the sic as the interrupt acknowledgement. the appropriate ilat register bit is set when an interrupt rising edge is detected (detection requ ires two core clock cycles). the bit is cleared when the respective ipend register bit is set. the ipend bit indicates that the event has entered into the proces- sor pipeline. at this point the cec will recognize and queue the next rising edge event on the corresponding event input. the minimum latency from the rising edge transition of the general- purpose interrupt to the ipend ou tput asserted is three core clock cycles; however, the latency can be much higher, depend- ing on the activity within and the state of the processor. dma controllers the adsp-bf534 processor has multiple, independent dma controllers that support automated data transfers with minimal overhead for the processor co re. dma transfers can occur between the adsp-bf534 processo r's internal memories and any of its dma-capable peripherals. additionally, dma trans- fers can be accomplished be tween any of the dma-capable peripherals and external device s connected to the external memory interfaces, including the sdram controller and the asynchronous memory controlle r. dma-capable peripherals include the sports, spi port, ua rts, and ppi. each individual dma-capable peripheral has at least one dedicated dma channel. the adsp-bf534 processor dm a controller supports both 1- dimensional (1d) and 2-dimensional (2d) dma transfers. dma transfer initialization can be implemented from registers or from sets of parameters called descriptor blocks. the 2d dma capability support s arbitrary row and column sizes up to 64k elements by 64k elements, and arbitrary row and column step sizes up to 32k elements. furthermore, the column step size can be less th an the row step size, allowing implementation of interleaved da ta streams. this feature is especially useful in video appl ications where data can be de- interleaved on the fly. examples of dma types support ed by the adsp-bf534 proces- sor dma controller include: ? a single, linear buffer that stops upon completion ? a circular, auto-refreshing buffer that interrupts on each full or fractionally full buffer ? 1-d or 2-d dma using a li nked list of descriptors ? 2-d dma using an array of descriptors, specifying only the base dma address wi thin a common page in addition to the dedicated peripheral dma channels, there are two memory dma channels provided for transfers between the various memories of the adsp-b f534 processor system. this enables transfers of blocks of data between any of the memo- riesincluding external sdram, rom, sram, and flash memorywith minimal processor intervention. memory dma transfers can be controlled by a very flexible descriptor-based methodology or by a standard register-based autobuffer mechanism. the adsp-bf534 processor also includes an external dma controller capability via dual ex ternal dma request pins when used in conjunction with the external bus interface unit (ebiu). this functionality can be used when a high speed inter- face is required for external fifos and high bandwidth communications peripherals such as usb 2.0. it allows control of the number of data transf ers for memdma. the number of transfers per edge is programmable. this feature can be pro- grammed to allow memdma to ha ve an increased priority on the external bus relative to the core. real-time clock (rtc) the adsp-bf534 processor real-t ime clock (rtc) provides a robust set of digital watch features, including current time, stop- watch, and alarm. the rtc is clocked by a 32.768 khz crystal external to the adsp-bf534 proc essor. the rtc peripheral has dedicated power supply pins so that it can remain powered up and clocked even when the rest of the processor is in a low- power state. the rtc provides several programmable interrupt options, including interrupt pe r second, minute, hour, or day clock ticks, interrupt on prog rammable stopwatch countdown, or interrupt at a programmed alarm time. the 32.768 khz input clock frequency is divided down to a 1 hz signal by a prescaler. the counter function of the timer consists of four counters: a 60-second counter, a 60-minute counter, a 24-hour counter, and an 32,768-day counter. when enabled, the alarm function generates an interrupt when the output of the timer matches the programmed value in the alarm control register. there are two alarms: the first alarm is for a time of day. the second alarm is for a day and time of that day.
adsp-bf534 preliminary technical data rev. pre | page 9 of 60 | july 2005 the stopwatch function counts down from a programmed value, with one-second resolu tion. when the stopwatch is enabled and the counter underflows, an interrupt is generated. like the other peripherals, th e rtc can wake up the adsp- bf534 processor from sleep mode upon generation of any rtc wakeup event. additionally, an rtc wakeup event can wake up the adsp-bf534 processor from deep sleep mode, and wake up the on-chip internal voltage regulator from the hibernate operating mode. connect rtc pins rtxi and rtxo with external components as shown in figure 4 . watchdog timer the adsp-bf534 processor includ es a 32-bit timer that can be used to implement a software watchdog function. a software watchdog can improve system avai lability by forcing the proces- sor to a known state through gene ration of a hardware reset, non-maskable interrupt (nmi), or general-purpose interrupt, if the timer expires before being reset by software. the program- mer initializes the count value of the timer, enables the appropriate interrupt, then enables the timer. thereafter, the software must reload the counter before it counts to zero from the programmed value. this prot ects the system from remain- ing in an unknown state where software, which would normally reset the timer, has stopped running due to an external noise condition or software error. if configured to generate a hardware reset, the watchdog timer resets both the core and the ad sp-bf534 processor peripherals. after a reset, software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in the watchdog timer control register. the timer is clocked by the system clock (sclk), at a maximum frequency of f sclk . timers there are nine general-purpose programmable timer units in the adsp-bf534 processor. eight timers have an external pin that can be configured either as a pulse width modulator (pwm) or timer output, as an inpu t to clock the timer, or as a mechanism for measuring pulse widths and periods of external events. these timers can be sync hronized to an external clock input to the several other associated pf pins, an external clock input to the ppi_clk input pin, or to the internal sclk. the timer units can be used in conjunction with the two uarts and the can controller to measur e the width of the pulses in the data stream to provide a soft ware auto-baud detect function for the respective serial channels. the timers can generate interrupt s to the processor core provid- ing periodic events for synchronization, either to the system clock or to a count of external signals. in addition to the eight genera l-purpose progra mmable timers, a ninth timer is also provided. th is extra timer is clocked by the internal processor clock and is ty pically used as a system tick clock for generation of operatin g system periodic interrupts. serial ports (sports) the adsp-bf534 processor incorporates two dual-channel synchronous serial ports (sport 0 and sport1) for serial and multiprocessor communications. the sports support the fol- lowing features: ?i 2 s capable operation. ? bidirectional operation C each sport has two sets of inde- pendent transmit and receive pins, enabling eight channels of i 2 s stereo audio. ? buffered (8-deep) transmit an d receive ports C each port has a data register for transfe rring data words to and from other processor components and shift registers for shifting data in and out of the data registers. ? clocking C each tran smit and receive port can either use an external serial clock or gene rate its own, in frequencies ranging from (f sclk /131,070) hz to (f sclk /2) hz. ? word length C each sport supports serial data words from 3 to 32 bits in length, tr ansferred most-significant-bit first or least-significant-bit first. ? framing C each transmit and receive port can run with or without frame sync signals for each data word. frame sync signals can be generated internally or externally, active high or low, and with either of tw o pulsewidths and early or late frame sync. ? companding in hardware C each sport can perform a-law or -law companding according to itu recommen- dation g.711. companding can be selected on the transmit and/or receive channel of the sport without additional latencies. ? dma operations with single-cycle overhead C each sport can automatically receive and tr ansmit multiple buffers of memory data. the processor can link or chain sequences of dma transfers between a sport and memory. figure 4. external components for rtc rtxo c1 c2 x1 suggested components: ecliptek ec38j (through-hole package) epson mc405 12 pf load (surface mount package) c1 = 22 pf c2 = 22 pf r1 = 10 m note: c1 and c2 are specific to crystal specified for x1. contact crystal manufacturer for details. c1 and c2 specifications assume board trace capacitance of 3 pf. rtxi r1
rev. pre | page 10 of 60 | july 2005 adsp-bf534 preliminary technical data ? interrupts C each transmit a nd receive port generates an interrupt upon completing the transfer of a data word or after transferring an entire data buffer or buffers through dma. ? multichannel capability C each sport supports 128 chan- nels out of a 1024-channel wind ow and is compatible with the h.100, h.110, mvip-90, and hmvip standards. serial peripheral interface (spi) port the adsp-bf534 processor has an spi-compatible port that enables the processor to commun icate with multiple spi-com- patible devices. the spi interface uses three pins for transferring data: two data pins (master output-slave input, mosi, and master input- slave output, miso) and a clock pin (serial clock, sck). an spi chip select input pin (spiss ) lets other spi devices select the processor, and seven spi chip select output pins (spisel7C1 ) let the processor select other spi de vices. the spi select pins are reconfigured programmable flag pins. using these pins, the spi port provides a full-duplex, sync hronous serial interface, which supports both master/slave modes and multimaster environments. the spi ports baud rate and clock phase/polarities are pro- grammable, and it has an integrated dma controller, configurable to support transmit or receive data streams. the spis dma controller can only se rvice unidirectional accesses at any given time. the spi ports clock rate is calculated as: where the 16-bit spi_baud regist er contains a value of 2 to 65,535. during transfers, the spi port simultaneously transmits and receives by serially shifting data in and out on its two serial data lines. the serial clock line sy nchronizes the shifting and sam- pling of data on the two serial data lines. uart ports (uarts) the adsp-bf534 processor provid es two full-duplex universal asynchronous receiver/transmitter (uart) ports, which are fully compatible with pc-stand ard uarts. each uart port provides a simplified uart inte rface to other peripherals or hosts, supporting full-duplex, dma-supported, asynchronous transfers of serial data. a uart port includes support for 5 to 8 data bits, 1 or 2 stop bits, and none, even, or odd parity. each uart port supports two modes of operation: ? pio (programmed i/o) C the processor sends or receives data by writing or reading i/o-mapped uart registers. the data is double-buffered on both transmit and receive. ? dma (direct memory access) C the dma controller transfers both transmit and receive data. this reduces the number and frequency of interr upts required to transfer data to and from memory. the uart has two dedicated dma channels, one for transmit and one for receive. these dma channels have lower defa ult priority than most dma channels because of their re latively low service rates. each uart port's baud rate, seri al data format, error code gen- eration and status, and interrupts are programmable: ? supporting bit rates ranging from (f sclk / 1,048,576) to (f sclk /16) bits per second. ? supporting data formats from 7 to12 bits per frame. ? both transmit and receive operations can be configured to generate maskable interrupts to the processor. the uart ports clock rate is calculated as: where the 16-bit uart_divisor comes from the dlh register (most significant 8 bits) and d ll register (least significant 8bits). in conjunction with the general-purpose timer functions, auto- baud detection is supported. the capabilities of the uarts are further extended with sup- port for the infrared data asso ciation (irda?) serial infrared physical layer link specification (sir) protocol. controller area network (can) the adsp-bf534 processor offers a can controller that is a communication controller implem enting the controller area network (can) 2.0b (active) protocol. this protocol is an asyn- chronous communications protocol used in both industrial and automotive control systems. the can protocol is well suited for control applications due to its capability to communicate reli- ably over a network since the protocol incorporates crc checking message error tracking, and fault node confinement. the adsp-bf534 can controller of fers the following features: ? 32 mailboxes (8 receive only , 8 transmit only, 16 config- urable for receive or transmit). ? dedicated acceptance masks for each mailbox. ? additional data filtering on first two bytes. ? support for both the standard (11-bit) and extended (29- bit) identifier (i d) message formats. ? support for remote frames. ? active or passive network support. ? can wakeup from hibernation mode (lowest static power consumption mode). ? interrupts, including: tx complete, rx complete, error, global. the electrical characteristics of each network connection are very demanding so the can interface is typically divided into two parts: a controller and a tran sceiver. this allows a single controller to support different drivers and can networks. the spi clock rate f sclk 2 spi_baud --------------------------------- = uart clock rate f sclk 16 uart_divisor ------------------------------------------------ =
adsp-bf534 preliminary technical data rev. pre | page 11 of 60 | july 2005 adsp-bf534 can module represen ts only the controller part of the interface. the controller interface supports connection to 3.3v high-speed, fault-tolera nt, single-wire transceivers. twi controller interface the adsp-bf534 processor incl udes a two wire interface (twi) module for providing a simple exchange method of con- trol data between multiple device s. the twi is compatible with the widely used i 2 c bus standard. the twi module offers the capabilities of simultaneous master and slave operation, sup- port for both 7-bit addressing and multimedia data arbitration. the twi interface utilizes two pins for transferring clock (scl) and data (sda) and supports the protocol at speeds up to 400k bits/sec. the twi interface pins are compatible with 5 v logic levels. additionally, the adsp-bf534 proc essors twi module is fully compatible with serial camera control bus (sccb) functional- ity for easier control of variou s cmos camera sensor devices. ports because of the rich set of peripherals, the adsp-bf534 proces- sor groups the many peripheral signals to four portsport f, port g, port h, and port j. mo st of the associated pins are shared by multiple signals. th e ports function as multiplexer controls. eight of the pins (port f7C0) offer high source/high sink current capabilities. general-purpose i/o (gpio) the adsp-bf534 processor has 48 bi-directional, general-pur- pose i/o (gpio) pins allocated across three separate gpio modules portfio, portgio, and porthio, associated with port f, port g, and port h, respectively. port j does not provide gpio functionality. ea ch gpio-capable pin shares functionality with other adsp-b f534 processor peripherals via a multiplexing scheme; however, the gpio functionality is the default state of the device upon power-up. neither gpio output or input drivers are active by de fault. each general-purpose port pin can be individually controlled by manipulation of the port control, status, and interrupt registers: ? gpio direction control register C specifies the direction of each individual gpio pin as input or output. ? gpio control and status registers C the adsp-bf534 processor employs a write one to modify mechanism that allows any combination of in dividual gpio pins to be modified in a single instruction, without affecting the level of any other gpio pins. four control registers are pro- vided. one register is written in order to set pin values, one register is written in order to clear pin values, one register is written in order to toggle pin values, and one register is written in order to specify a pin value. reading the gpio status register allows software to interrogate the sense of the pins. ? gpio interrupt mask register s C the two gpio interrupt mask registers allow each individual gpio pin to function as an interrupt to the processor. similar to the two gpio control registers that are used to set and clear individual pin values, one gpio interrupt mask register sets bits to enable interrupt function, an d the other gpio interrupt mask register clears bits to disable interrupt function. gpio pins defined as inputs can be configured to generate hardware interrupts, while output pins can be triggered by software interrupts. ? gpio interrupt sensitivity registers C the two gpio interrupt sensitivity registers specify whether individual pins are level- or edge-sensiti ve and specifyif edge-sensi- tivewhether just the rising edge or both the rising and falling edges of the signal ar e significant. one register selects the type of sensitivity, and one register selects which edges are significant for edge-sensitivity. parallel peripheral interface (ppi) the adsp-bf534 processor prov ides a parallel peripheral interface (ppi) that can connec t directly to parallel a/d and d/a converters, itu-r-601/656 vi deo encoders and decoders, and other general-purpose periph erals. the ppi consists of a dedicated input clock pin, up to 3 frame synchronization pins, and up to 16 data pins. in itu-r-656 modes, the ppi receiv es and parses a data stream of 8-bit or 10-bit data elements . on-chip decode of embedded preamble control and synchronization information is supported. three distinct itu-r- 656 modes are supported: ?active video only modethe ppi does not read in any data between the end of active video (eav) and start of active video (sav) preamble symbols, or any data present during the vertical blanking intervals. in this mode, the control byte sequences are not stored to memory; they are filtered by the ppi. ? vertical blanking only mode the ppi only transfers ver- tical blanking interval (vbi) data, as well as horizontal blanking information and control byte sequences on vbi lines. ? entire field modethe entire incoming bitstream is read in through the ppi. this includes active video, control pre- amble sequences, and ancillary data that may be embedded in horizontal and vertical blanking intervals. though not explicitly supported, itu-r-656 output functional- ity can be achieved by setting up the entire frame structure (including active video, blanking, and control information) in memory and streaming the data ou t the ppi in a frame sync-less mode. the processors 2d dma feat ures facilitate this transfer by allowing the static frame buffer (blanking and control codes) to be placed in memory once, and simply updating the active video information on a per-frame basis. the general-purpose modes of the ppi are intended to suit a wide variety of data capture and transmission applications. the modes are divided into four main categories, each allowing up to 16 bits of data tran sfer per ppi_clk cycle: ? data receive with interna lly generated frame syncs. ? data receive with externally generated frame syncs.
rev. pre | page 12 of 60 | july 2005 adsp-bf534 preliminary technical data ? data transmit with internally generated frame syncs ? data transmit with externally generated frame syncs these modes support adc/dac connections, as well as video communication with hardware signalling. many of the modes support more than one level of frame synchronization. if desired, a programmable delay can be inserted between asser- tion of a frame sync and reception/transmission of data. dynamic power management the adsp-bf534 processor prov ides five operating modes, each with a different performanc e/power profile. in addition, dynamic power management provides the control functions to dynamically alter the processor core supply voltage, further reducing power dissipation. control of clocking to each of the adsp-bf534 processor peripher als also reduces power con- sumption. see table 4 for a summary of the power settings for each mode. full-on operating mode C maximum performance in the full-on mode, the pll is enabled and is not bypassed, providing capability for maximum operational frequency. this is the power-up default execut ion state in which maximum per- formance can be achieved. the processor core and all enabled peripherals run at full speed. active operating mode C moderate power savings in the active mode, the pll is enabled but bypassed. because the pll is bypassed, the processors core clock (cclk) and sys- tem clock (sclk) run at the input clock (clkin) frequency. in this mode, the clkin to cclk multiplier ratio can be changed, although the changes are not real ized until the full-on mode is entered. dma access is available to appropriately configured l1 memories. in the active mode, it is possible to disable the pll through the pll control register (pll_ctl). if disabled, the pll must be re-enabled before transitioning to the full-on or sleep modes. sleep operating mode C high dynamic power savings the sleep mode reduces dynami c power dissipation by dis- abling the clock to the proce ssor core (cclk). the pll and system clock (sclk), however, continue to operate in this mode. typically an external even t or rtc activity will wake up the processor. when in the slee p mode, assertion of wakeup will cause the processor to sense the value of the bypass bit in the pll control register (pll_ctl). if bypass is disabled, the processor will transition to th e full on mode. if bypass is enabled, the processor will tran sition to the active mode. when in the sleep mode, system dma access to l1 memory is not supported. deep sleep operating mode C maximum dynamic power savings the deep sleep mode maximize s dynamic powe r savings by disabling the clocks to the proce ssor core (cclk) and to all syn- chronous peripherals (sclk). as ynchronous peripherals, such as the rtc, may still be running but will not be able to access internal resources or external memory. this powered-down mode can only be exited by as sertion of the reset interrupt (reset ) or by an asynchronous interrupt generated by the rtc. when in deep sleep mode , an rtc asynchronous inter- rupt causes the processor to tr ansition to the active mode. assertion of reset while in deep sleep mode causes the pro- cessor to transition to the full on mode. hibernate operating mode C maximum static power savings the hibernate mode maximizes static power savings by dis- abling the voltage and clocks to the processor core (cclk) and to all the synchronous peripheral s (sclk). the internal voltage regulator for the processor can be shut off by writing b#00 to the freq bits of the vr_ctl register. this disables both cclk and sclk. furthermore, it sets the internal power supply volt- age (v ddint ) to 0v to provide the greatest power savings mode. any critical information stored internally (memory contents, register contents, etc.) must be written to a non-volatile storage device prior to removing power if the processor state is to be preserved. since v ddext is still supplied in this mode, all of the external pins tri-state, unless otherwise specified. this allows other devices that may be connected to the processor to have power still applied without drawing unwanted current. the internal supply regulator can be woken up by can. it can also be woken up by a real-time clock wakeup event or by asserting the reset pin, both of which initiate the hardware reset sequence. with the exception of the vr_ctl and the rtc registers, all internal registers and memories lose their content in hibernate state. state variables may be held in external sram or sdram. the ckelow bit in the vr_ctl register controls whether sdram operates in self-refresh mo de to retain its content while the processor is in reset. power savings as shown in table 5 , the adsp-bf534 proc essor supports three different power domains. the use of multiple power domains maximizes flexibility, while maintaining compliance with industry standards and convention s. by isolating the internal logic of the adsp-bf534 processo r into its own power domain, separate from the rtc and othe r i/o, the processor can take table 4. power settings mode pll pll bypassed core clock (cclk) system clock (sclk) core power full on enabled no enabled enabled on active enabled/ disabled yes enabled enabled on sleep enabled - disabled enabled on deep sleep disabled - disabled disabled on hibernate disabled - disabled disabled off
adsp-bf534 preliminary technical data rev. pre | page 13 of 60 | july 2005 advantage of dynamic power management, without affecting the rtc or other i/o devices. th ere are no sequencing require- ments for the various power domains. the power dissipated by a processo r is largely a function of the clock frequency of the processor and the square of the operating voltage. for example, reducing the clock frequency by 25% results in a 25% reduction in power dissipation, while reducing the voltage by 25% reduces powe r dissipation by more than 40%. further, these power savings are additive, in that if the clock frequency and supply voltage are both reduced, the power savings can be dramatic. the dynamic power management feature of the adsp-bf534 processor allows both the processors input voltage (v ddint ) and clock frequency (f cclk ) to be dynamically controlled. as explained above, the savings in power dissipation can be modeled by the following equations: where the variables in the equations are: ?f cclknom is the nominal core clock frequency ?f cclkred is the reduced core clock frequency ?v ddintnom is the nominal internal supply voltage ?v ddintred is the reduced internal supply voltage ?t nom is the duration running at f cclknom ?t red is the duration running at f cclkred voltage regulation the adsp-bf534 processor provides an on-chip voltage regula- tor that can generate processor core voltage levels (0.85v to 1.2v guaranteed from -5% to 10% ) from an external 2.25 v to 3.6 v supply. figure 5 shows the typical external components required to complete the powe r management system. the regu- lator controls the internal logic voltage levels and is programmable with the voltag e regulator control register (vr_ctl) in increments of 50 mv. to reduce standby power consumption, the internal voltag e regulator can be programmed to remove power to the processo r core while keeping i/o power supplied. while in hibernate mode, v ddext can still be applied, eliminating the need for external buffers. the voltage regulator can be activated from this power down state by assertion of the reset pin, which will then initiate a boot sequence. the regula- tor can also be disabled and by passed at the users discretion. clock signals the adsp-bf534 processor can be clocked by an external crys- tal, a sine wave input, or a buffered, shaped clock derived from an external clock oscillator. if an external clock is used, it should be a ttl compatible signal and must not be halted, changed, or operated below the speci- fied frequency during normal operation. this signal is connected to the processors cl kin pin. when an external clock is used, the xtal pin must be left unconnected. alternatively, because the adsp -bf534 processor includes an on-chip oscillator circuit, an ex ternal crystal may be used. for fundamental frequency operatio n, use the circuit shown in figure 6 . a parallel-resonant, fund amental frequency, micro- processor-grade crystal is co nnected across the clkin and xtal pins. the on-chip resist ance between clkin and the xtal pin is in the 500 kohm ra nge. further parallel resistors are typically not recommended. the two capacitors and the series resistor shown in figure 6 fine tune phase and amplitude of the sine frequency. the capacitor and resist or values shown in figure 6 are typical values only. the capacitor values are dependent upon the crystal manufacturers load capacitance recommendations and the pcb physical layout. the resistor va lue depends on the drive level table 5. power domains power domain vdd range all internal logic, except rtc v ddint rtc internal logic and crystal i/o v ddrtc all other i/o v ddext power savings factor f cclkred f cclknom ------------------------------- - v ddintred v ddintnom -------------------------------------- ?? ?? ?? 2 t red t nom ----------------- - ? ? ? ? ? ? = % power savings 1 po wer savings factor ? () 100% = figure 5. voltage regulator circuit v ddext v ddint vr out 1-0 external components 2.25v - 3.6v input voltage range fds9431a zhcs1000 100 f 1f 10 h 0.1 f note: vr out 1-0 should be tied together externally and designer should minimize trace length to fds9431a. 100 f
rev. pre | page 14 of 60 | july 2005 adsp-bf534 preliminary technical data specified by the crystal manufactur er. the user should verify the customized values based on care ful investigations on multiple devices over temperature range. if the user prefers, a third-over tone crystal can be used at fre- quencies above 25 mhz. the circui t is then modified to ensure crystal operation only at the third overtone, by adding a tuned inductor circuit as shown in figure 6 . a design procedure for third-overtone operation is disc ussed in detail in application note ee-168. the clkbuf pin is an output pin, and is a buffer version of the input clock. the blackfin core is running at a different clock rate than the on-chip peripherals. as shown in figure 7 on page 14 , the core clock (cclk) and system peripheral clock (sclk) are derived from the input clock (clkin) signal. an on-chip pll is capable of multiplying the clkin signal by a user programma- ble 1x to 63x multiplication factor (bounded by specified minimum and maximum vco frequencies). the default multi- plier is 10x, but it can be modified by a software instruction sequence. on-the-fly frequency ch anges can be effected by sim- ply writing to the pll_div register. the clkbuf output is active by default and can be disa bled by the vr_ctl register for power savings. on-the-fly cclk and sclk freq uency changes can be effected by simply writing to the pll_d iv register. whereas the maxi- mum allowed cclk and sclk rates depend on the applied voltages v ddint and v ddext , the vco is always permitted to run up to the frequency specified by the parts speed grade. the clkout pin reflects the sclk frequency to the off-chip world. it belongs to the sdram interface, but it functions as reference signal in other timing specifications as well. while active by default, it can be disabled by the ebiu_sdgctl and ebiu_amgctl registers. all on-chip peripherals are clocked by the system clock (sclk). the system clock frequency is programmable by means of the ssel3C0 bits of the pll_div re gister. the values programmed into the ssel fields define a divide ratio between the pll output (vco) and the system clock. sclk divider values are 1 through 15. table 6 illustrates typical system clock ratios: note that the divisor ratio must be chosen to limit the system clock frequency to its maximum of f sclk . the ssel value can be changed dynamically without any pll lock latencies by writing the appropriate values to the pll divisor register (pll_div). the core clock (cclk) freque ncy can also be dynamically changed by means of the csel1C0 bits of the pll_div register. supported cclk divider ratios are 1, 2, 4, and 8, as shown in table 7 . this programmable core cloc k capability is useful for fast core frequency modifications. the maximum cclk frequency not only depends on the part's speed grade (see page 59 ), it also depends on the applied v ddint voltage. see table 10 - table 11 for details. the maximal system clock rate (sclk) depends on th e chip package and the applied v ddext voltage (see table 13 ). figure 6. external crystal connections clkin clkout xtal en clkbuf to pll circuitry for overtone operation only: note: values marked with * must be customized depending on the crystal and layout. please analyze carefully. 18 pf* en 18 pf* 330 * blackfin figure 7. frequency mo dification methods table 6. example system clock ratios signal name ssel3C0 divider ratio vco/sclk example frequency ratios (mhz) vco sclk 0001 1:1 100 100 0110 6:1 300 50 1010 10:1 500 50 table 7. core clock ratios signal name csel1C0 divider ratio vco/cclk example frequency ratios vco cclk 00 1:1 300 300 01 2:1 300 150 10 4:1 500 125 11 8:1 200 25 pll .5x - 64x + 1:15 + 1 , 2, 4, 8 vco sclk cclk sclk 133 mhz clkin dynamic modification re qui re s pll seq uencing dynamic mo dificatio n on-the-fly cclk sclk
adsp-bf534 preliminary technical data rev. pre | page 15 of 60 | july 2005 booting modes the adsp-bf534 processor has six mechanisms (listed in table 8 ) for automatically loading internal and external mem- ory after a reset. a seventh mode is provided to execute from external memory, bypassing the boot sequence. the bmode pins of the reset configuration register, sampled during power-on resets and so ftware-initiated resets, imple- ment the following modes: ? execute from 16-bit external memory C execution starts from address 0x2000 0000 with 16-bit packing. the boot rom is bypassed in this mode. all configuration settings are set for the slowest device possible (3-cycle hold time; 15-cycle r/w access time s; 4-cycle setup). ? boot from 8-bit and 16-bit external flash memory C the 8-bit or 16-bit flash boot routine located in boot rom memory space is set up usin g asynchronous memory bank 0. all configuration settings ar e set for the slowest device possible (3-cycle hold time; 15-cycle r/w access times; 4-cycle setup). the boot rom evaluates the first byte of the boot stream at address 0x2000 0000. if it is 0x40, 8-bit boot is performed. a 0x60 byte as sumes a 16-bit memory device and performs 8-bit dma. a 0x 20 byte also assumes 16-bit memory but performs 16-bit dma. ? boot from serial spi memory (eeprom or flash). 8-, 16-, or 24-bit addressable devices are supported as well as are at45db041, at45db081, at45db161, at45db321, at45db642, and at45db1282 dataflash ? devices from atmel. the spi uses the pf10/spi ssel1 output pin to select a single spi eeprom/fl ash device, submits a read command and successive address bytes (0x00) until a valid 8-, 16-, or 24-bit, or atmel ad dressable device is detected, and begins clocking data into the processor. ? boot from spi host device C the blackfin processor oper- ates in spi slave mode and is configured to receive the bytes of the .ldr file from an spi host (master) agent. to hold off the host device from transmitting while the boot rom is busy, the blackfin processor will assert a gpio pin, called host wait (hwait), to signal the host device not to send any more bytes until the flag is de-asserted. the flag is cho- sen by the user and this information will be transferred to the blackfin processor via bits 10:5 of the flag header. ? boot from uart C using an autobaud handshake sequence, a boot-stream-forma tted program is downloaded by the host. the host agent se lects a baud rate within the uarts clocking capabilities. when performing the auto- baud, the uart expects a @ (boot stream) character (eight bits data, one start bit, one stop bit, no parity bit) on the rxd pin to determine the bit rate. it then replies with an acknowledgement which is composed of 4 bytes: 0xbf, the value of uart_dll, the value of uart_dlh, 0x00. the host can then download the boot stream. when the processor needs to hold off the host, it de-asserts cts. therefore, the host must monitor this signal. ? boot from serial twi memory (eeprom/flash) C the blackfin processor operates in master mode and selects the twi slave with the unique id 0xa0. it submits successive read commands to the memory device starting at two byte internal address 0x 0000 and begins clocking data into the processor. the twi memory de vice should comply with philips i 2 c bus specification version 2.1 and have the capa- bility to auto-increment its internal address counter such that the contents of the me mory device can be read sequentially. ? boot from twi host C the twi host agent selects the slave with the unique id 0x5f. the processor replies with an acknowledgement and the host can then download the boot stream. the twi host agent should comply with philips i 2 c bus specification version 2.1. an i 2 c multi- plexer can be used to select one processor at a time when booting multiple processors from a single twi. for each of the boot modes, a 10-byte header is first brought in from an external device. the he ader specifies the number of bytes to be transferred and th e memory destin ation address. multiple memory blocks may be loaded by any boot sequence. once all blocks are loaded, pr ogram execution commences from the start of l1 instruction sram. in addition, bit 4 of the reset configuration register can be set by application code to bypass th e normal boot sequence during a software reset. for this case, the processor jumps directly to the beginning of l1 instruction memory. to augment the boot modes, a se condary software loader can be added to provide additional booting mechanisms. this second- ary loader could provide the capability to boot from flash, variable baud rate, and other sour ces. in all boot modes except bypass, program execution star ts from on-chip l1 memory address 0xffa0 0000. instruction set description the blackfin processor family a ssembly language instruction set employs an algebraic syntax designed for ease of coding and readability. the instructions have been specifically tuned to pro- vide a flexible, densely encoded instruction set that compiles to a very small final memory size. th e instruction set also provides fully featured multifunction in structions that allow the pro- table 8. booting modes bmode2C0 description 000 execute from 16-bit external memory (bypass boot rom) 001 boot from 8-bit or 16-bit memory (eprom/flash) 010 reserved 011 boot from serial sp i memory (eeprom/flash) 100 boot from spi ho st (slave mode) 101 boot from serial twi memory (eeprom/flash) 110 boot from twi host (slave mode) 111 boot from uart host (slave mode)
rev. pre | page 16 of 60 | july 2005 adsp-bf534 preliminary technical data grammer to use many of the proce ssor core resources in a single instruction. coupled with many features more often seen on microcontrollers, this instruction set is very efficient when com- piling c and c++ source code. in addition, the architecture supports both user (algorithm/a pplication code) and supervisor (o/s kernel, device drivers, debuggers, isrs) modes of opera- tion, allowing multiple levels of access to core processor resources. the assembly language, which takes advantage of the proces- sors unique architecture, offers the following advantages: ? seamlessly integrated dsp/mcu features are optimized for both 8-bit and 16-bit operations. ? a multi-issue load/store modified-harvard architecture, which supports two 16-bit mac or four 8-bit alu + two load/store + two pointer updates per cycle. ? all registers, i/o, and memory are mapped into a unified 4g byte memory space, providing a simplified program- ming model. ? microcontroller features, such as arbitrary bit and bit-field manipulation, insertion, and ex traction; integer operations on 8-, 16-, and 32-bit data-typ es; and separate user and supervisor stack pointers. ? code density enhancements, wh ich include intermixing of 16- and 32-bit instructions (no mode switching, no code segregation). frequently used instructions are encoded in 16 bits. development tools the adsp-bf534 processor is suppo rted with a complete set of crosscore? software and ha rdware development tools, including analog devices emulators and visualdsp++? devel- opment environment. the same emulator hardware that supports other blackfin processors also fully emulates the adsp-bf534 processor. ez-kit lite evaluation board for evaluation of adsp-bf534 processors, use the adsp- bf537 ez-kit lite boar d available from anal og devices. order part number adds-bf537-ezlite . the board comes with on- chip emulation capabilities and is equipped to enable software development. multiple daug hter cards are available. designing an emulator-compatible processor board (target) the analog devices family of em ulators are tools that every sys- tem developer needs to test and debug hardware and software systems. analog devices has supplied an ieee 1149.1 jtag test access port (tap) on each jtag processor. the emulator uses the tap to access the internal features of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. the proces- sor must be halted to send da ta and commands, but once an operation has been completed by the emulator, the processor system is set running at full sp eed with no impact on system timing. to use these emulators, the target board must include a header that connects the processors jtag port to the emulator. for details on target board desi gn issues including mechanical layout, single processor conne ctions, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see analog devices jtag emul ation technical reference (ee-68) on the analog devices web site under www.analog.com/ee-notes . this document is updated regularly to keep pace with improvements to emulator support. related documents the following publications that describe the adsp-bf534 pro- cessors (and related processors) can be ordered from any analog devices sales office or accessed electronically on our web site: ? getting started with blackfin processors ? adsp-bf537 blackfin proc essor hardware reference ? adsp-bf53x/bf56x blackfin processor programming reference ? adsp-bf534 blackfin processor anomaly list
adsp-bf534 preliminary technical data rev. pre | page 17 of 60 | july 2005 pin descriptions adsp-bf534 processor pin de finitions are listed in table 9 . in order to maintain maximum functionality and reduce package size and pin count, some pins have dual, multiplexed function- ality. in cases where pin functionality is reconfigurable, the default state is shown in plain text, while alternate functionality is shown in italics. pins shown wi th an asterisk after their name (*) offer high source/high sink current capabilities. all pins are tristated during and immediately after reset with the exception of the external memory interface. on the external memory interface, the control an d address lines are driven high during reset unless the br pin is asserted. all i/o pins have their input buffers disabled with the exception of the pins noted in the data sheet that need pullups or pull- downs if unused. table 9. pin descriptions pin name i/o function driver type 1 memory interface addr19C1 o address bus for async access a data15C0 i/o data bus for async/sync access a abe1C0 /sdqm1C0 o byte enables/data masks for async/sync access a br 2 ibus request bg obus grant a bgh o bus grant hang a asynchronous memory control ams3C0 o bank select a ardy i hardware ready control aoe o output enable a are oread enable a awe owrite enable a synchronous memory control sras o row address strobe a scas o column address strobe a swe owrite enable a scke o clock enable a clkout o clock output b sa10 o a10 pin a sms o bank select a port f: gpio/uart1C0/timer7C0/external dma request (* = high source/high sink pin) pf0* - gpio/ uart0 tx / dmar0 i/o gpio/ uart0 transmit / dma request 0 c pf1*- gpio/ uart0 rx / dmar1 / taci1 i/o gpio/ uart0 receive / dma request 1 / timer1 alternate input capture c pf2* - gpio/ uart1 tx / tmr7 i/o gpio/ uart1 transmit / timer7 c pf3* - gpio/ uart1 rx / tmr6 / taci6 i/o gpio/ uart1 receive / timer6 / timer6 alternate input capture c pf4* - gpio/ tmr5 / spi ssel6 i/o gpio/ timer5 / spi slave select enable 6 c pf5* - gpio/ tmr4 / spi ssel5 i/o gpio/ timer4 / spi slave select enable 5 c pf6* - gpio/ tmr3 / spi ssel4 i/o gpio/ timer3 / spi slave select enable 4 c pf7* - gpio/ tmr2 / ppi fs3 i/o gpio/ timer2 / ppi frame sync 3 c pf8 - gpio/ tmr1 / ppi fs2 i/o gpio/ timer1 / ppi frame sync 2 d pf9 - gpio/ tmr0 / ppi fs1 i/o gpio/ timer0 / ppi frame sync 1 d pf10 - gpio/ spi ssel1 i/o gpio/ spi slave select enable 1 d pf11 - gpio/ spi mosi i/o gpio/ spi master out slave in d
rev. pre | page 18 of 60 | july 2005 adsp-bf534 preliminary technical data port f: gpio/uart1C0/timer7C0/external dma request (* = high source/high sink pin), continued pf12 - gpio/ spi miso 3 i/o gpio/ spi master in slave out d pf13 - gpio/ spi sck i/o gpio/ spi clock d pf14 - gpio/ spi ss / taclk0 i/o gpio/ spi slave select / alternate timer0 clock input d pf15 - gpio/ ppi clk / tmrclk i/o gpio/ ppi clock / external timer reference d port g: gpio/ppi/sport1 pg0 - gpio/ ppi d0 i/o gpio/ ppi data 0 d pg1 - gpio/ ppi d1 i/o gpio/ ppi data 1 d pg2 - gpio/ ppi d2 i/o gpio/ ppi data 2 d pg3 - gpio/ ppi d3 i/o gpio/ ppi data 3 d pg4 - gpio/ ppi d4 i/o gpio/ ppi data 4 d pg5 - gpio/ ppi d5 i/o gpio/ ppi data 5 d pg6 - gpio/ ppi d6 i/o gpio/ ppi data 6 d pg7 - gpio/ ppi d7 i/o gpio/ ppi data 7 d pg8 - gpio/ ppi d8 / dr1sec i/o gpio/ ppi data 8 / sport1 receive data secondary d pg9 - gpio/ ppi d9 / dt1sec i/o gpio/ ppi data 9 / sport1 transmit data secondary d pg10 - gpio/ ppi d10 / rsclk1 i/o gpio/ ppi data 10 / sport1 receive serial clock d pg11 - gpio/ ppi d11 / rfs1 i/o gpio/ ppi data 11 / sport1 receive frame sync d pg12 - gpio/ ppi d12 / dr1pri i/o gpio/ ppi data 12 / sport1 receive data primary d pg13 - gpio/ ppi d13 / tsclk1 i/o gpio/ ppi data 13 / sport1 transmit serial clock d pg14 - gpio/ ppi d14 / tfs1 i/o gpio/ ppi data 14 / sport1 transmit frame sync d pg15 - gpio/ ppi d15 / dt1pri i/o gpio/ ppi data 15 / sport1 transmit data primary d port h: gpio ph0 - gpio i/o gpio d ph1 - gpio i/o gpio d ph2 - gpio i/o gpio d ph3 - gpio i/o gpio d ph4 - gpio i/o gpio d ph5 - gpio i/o gpio d ph6 - gpio i/o gpio d ph7 - gpio i/o gpio d ph8 - gpio i/o gpio d ph9 - gpio i/o gpio d ph10 - gpio i/o gpio d ph11 - gpio i/o gpio d ph12 - gpio i/o gpio d ph13 - gpio i/o gpio d ph14 - gpio i/o gpio d ph15 - gpio i/o gpio d table 9. pin descriptions (continued) pin name i/o function driver type 1
adsp-bf534 preliminary technical data rev. pre | page 19 of 60 | july 2005 port j:sport0/twi/spi select/can pj0 - no connect no connect pj1 - connect to gnd g connect to gnd pj2 - scl i/o twi serial clock d pj3 - sda i/o twi serial data d pj4 - dr0sec/ canrx / taci0 i sport0 receive data secondary/ can receive / timer0 alternate input capture pj5 - dt0sec/ cantx / spi ssel7 o sport0 transmit data secondary/ can transmit / spi slave select enable 7 d pj6 - rsclk0/ taclk2 i/o sport0 receive serial clock/ alternate timer2 clock input e pj7 - rfs0/ taclk3 i/o sport0 receive frame sync/ alternate timer3 clock input d pj8 - dr0pri/ taclk4 i sport0 receive data primary/ alternate timer4 clock input pj9 - tsclk0/ taclk1 i/o sport0 transmit serial clock/ alternate timer1 clock input e pj10 - tfs0/ spi ssel3 i/o sport0 transmit frame sync/ spi slave select enable 3 d pj11 - dt0pri/ spi ssel2 o sport0 transmit data primary/ spi slave select enable 2 d real time clock rtxi 4 i rtc crystal input rtxo o rtc crystal output jtag port tck i jtag clock tdo o jtag serial data out d tdi i jtag serial data in tms i jtag mode select trst 5 ijtag reset emu o emulation output d clock clkin i clock/crystal input xtal o crystal output clkbuf o buffered clkin output mode controls reset i reset nmi 6 i non-maskable interrupt bmode2C0 i boot mode strap 2-0 voltage regulator vrout0 o external fet drive vrout1 o external fet drive supplies v ddext pi/o power supply v ddint p internal power supply (regulated from 2.25v to 3.6v) v ddrtc p real time clock power supply gnd g external ground 1 see output drive currents on page 46 for more information about each driver types. 2 this pin should be pulled high when not used. 3 this pin should always be pulled high through a 4.7 k ohms resist or if booting via the spi port. 4 this pin should always be pulled low when not used. 5 this pin should be pulled low if the jtag port will not be used. 6 this pin should always be pulled high when not used. table 9. pin descriptions (continued) pin name i/o function driver type 1
rev. pre | page 20 of 60 | july 2005 adsp-bf534 preliminary technical data specifications note that component specificat ions are subject to change without notice. recommended operating conditions parameter 1 1 specifications subject to change without notice. minimum nominal maximum unit v ddint internal supply voltage 2 (400 mhz) 2 voltage regulator output is guaranteed from -5% to 10% of specified values. 0.8 1.2 1.32 v v ddint internal supply voltage 2 (500 mhz) 0.8 1.26 1.32 v v ddext external supply voltage 2.25 2.5 or 3.3 3.6 v v ddrtc real time clock power supply voltage 2.25 3.6 v v ih high level input voltage 3, 4 , @ v ddext =maximum 3 the adsp-bf534 processor is 3.3 v tolera nt (always accepts up to 3.6 v maximum v ih ), but voltage compliance (on outputs, v oh ) depends on the input v ddext , because v oh (maximum) approximately equals v ddext (maximum). this 3.3 v tolerance applie s to bi-directional pins (d ata15C0, pf15C0, pg1 5C0, ph15C0, tfs0, tclk0, rsclk0, rfs0) and input only pins (br , ardy, dr0pri, dr0sec, rtxi, tck, tdi, tms, trst , clkin, reset , nmi , and bmode2C0). 4 parameter value applies to all input and bi-directional pins except clkin, sda, and scl. 2.0 3.6 v v ihclkin high level input voltage 5 , @ v ddext =maximum 5 parameter value applies to clkin pin only. 2.2 3.6 v v ih5v high level input voltage 6 , @ v ddext =maximum 6 certain adsp-bf534 processor pins are 5.0 v tole rant (always accept up to 5.5 v maximum v ih ), but voltage compliance (on outputs, v oh ) depends on the input v ddext , because v oh (maximum) approximately equals v ddext (maximum). this 5.0 v tolerance a pplies to sda and scl pins only. the sda and scl pins are open drain and therefore require a pullup resistor. consult the i 2 c specification version 2.1 fo r the proper resistor value. 2.0 5.0 v v il low level input voltage 3, 7 , @ v ddext =minimum 7 parameter value applies to all input and bi-directional pins except sda and scl. C0.3 0.6 v v il5v low level input voltage 6 , @ v ddext =minimum C0.3 0.8 v t a ambient operating temperature automotive C40 105 oc industrial C40 85 oc
adsp-bf534 preliminary technical data rev. pre | page 21 of 60 | july 2005 electrical characteristics parameter 1 1 specifications subject to change without notice. test conditions min max unit v oh high level output voltage 2 2 applies to output an d bidirectional pins. port f7C0 @ v ddext = 3.3v +/- 10%, i oh = C10 ma @ v ddext = 2.5v +/- 10%, i oh = C6 ma v ddext C 0.5v v ddext C 0.5v v v port f15C8, port g, port h i oh = C1 ma v ddext C 0.5v v max combined for port f7C0 tbd v max total for all port f, port g, and port h pins tbd v v ol low level output voltage 2 port f7C0 @ v ddext = 3.3v +/- 10%, i ol = 10 ma @ v ddext = 2.5v +/- 10%, i ol = 6 ma 0.5v 0.5v v v port f15C8, port g, port h i ol = 2 ma 0.5v v max combined for port f7C0 tbd v max total for all port f, port g, and port h pins tbd v i ih high level input current 3 3 applies to input pins. @ v ddext =maximum, v in = v dd maximum tbd a i il low level input current 4 @ v ddext =maximum, v in = 0 v tbd a i ozh three-state leakage current 4 4 applies to three-statable pins. @ v ddext = maximum, v in = v dd maximum tbd a i ozl three-state leakage current 5 @ v ddext = maximum, v in = 0 v tbd a max total current for all port f, port g, and port h pins tbd ma c in input capacitance 5, 6 5 applies to all signal pins. 6 guaranteed, but not tested. f in = 1 mhz, t a mbient = 25c, v in = 2.5 v tbd pf
rev. pre | page 22 of 60 | july 2005 adsp-bf534 preliminary technical data absolute maximum ratings esd sensitivity internal (core) supply voltage 1 (v ddint ) 1 stresses greater than those listed above may cause permanent damage to the device. these are stress ratings only. function al operation of the device at these or any other conditions greater than those indicated in the operational se ctions of this specific ation is not implied. exposure to absolute maximum ra ting conditions for extended periods may affect device reliability. C0.3 v to +1.4 v external (i/o) supply voltage 1 (v ddext )C0.3 v to +3.8 v input voltage 1 C0.5 v to +3.6 v output voltage swing 1 C0.5 v to v ddext +0.5 v load capacitance 1,2 2 for proper sdram controller operation, the maximum load capacitance is 50 pf (at 3.3v) or 30 pf (at 2.5v) for addr19C1, data15C0, abe1C0 /sdqm1C0, clkout, scke, sa10, sras , scas , swe , and sms . 200 pf storage temperature range 1 C65oc to +150oc junction temperature underbias 1 +125oc figure 8. product information on package 367334.1 0.2 silicon revision lot number bbcz-5b1 product date code assembly b = temp range bc = mini bga z=leadfree 5 = speed grade b1= package type b adsp-bf534 a 0440 singapore caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000v readily accumulate on the human body and test equipment and can discharg e without detection. although the adsp-bf534 processor features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electr ostatic discharges. therefore, proper esd precau- tions are recommended to avoid performance degradation or loss of functionality.
adsp-bf534 preliminary technical data rev. pre | page 23 of 60 | july 2005 timing specifications table 10 and table 11 describe the timing requirements for the adsp-bf534 processor clocks. t ake care in selecting msel, ssel, and csel ratios so as no t to exceed the maximum core clock and system clock. table 12 describes phase-locked loop operating conditions. table 10. core clock requirements500 mhz speed grade 1 parameter minimum maximum unit f cclk core clock frequency (v ddint =1.2 v minimum) 500 mhz f cclk core clock frequency (v ddint =1.045 v minimum) tbd mhz f cclk core clock frequency (v ddint =0.95 v minimum) tbd mhz f cclk core clock frequency (v ddint =0.85 v minimum) tbd mhz f cclk core clock frequency (v ddint =0.8 v) tbd mhz 1 the speed grade of a given part is printed on the ch ips package as shown in figure 8 on page 22 and can also be seen on the ordering guide on page 59 . it stands for the maximum allowed cclk frequency at vddint = 1.2v and the maximum allowed vco frequency at any supply voltage. table 11. core clock requirements400 mhz speed grade 1 parameter minimum maximum unit f cclk core clock frequency (v ddint =1.14 v minimum) 400 mhz f cclk core clock frequency (v ddint =1.045 v minimum) tbd mhz f cclk core clock frequency (v ddint =0.95 v minimum) tbd mhz f cclk core clock frequency (v ddint =0.85 v minimum) tbd mhz f cclk core clock frequency (v ddint =0.8 v) tbd mhz 1 the speed grade of a given part is printed on the ch ips package as shown in figure 8 on page 22 and can also be seen on the ordering guide on page 59 . it stands for the maximum allowed cclk frequency at vddint = 1.2v and the maximum allowed vco frequency at any supply voltage. table 12. phase-locked loop operating conditions parameter minimum maximum unit f vco voltage controlled oscillator (vco) frequency 50 speed grade 1 mhz 1 the speed grade of a given part is printed on the ch ips package as shown in figure 8 on page 22 and can also be seen on the ordering guide on page 59 . it stands for the maximum allowed cclk frequency at vddint = 1.2v and the maximum allowed vco frequency at any supply voltage. table 13. system clock requirements parameter condition minimum maximum unit 182 mbga f sclk v ddext = 3.3 v, v ddint >= tbd v tbd mhz f sclk v ddext = 3.3 v, v ddint < tbd v tbd mhz f sclk v ddext = 2.5 v, v ddint >= tbd v tbd mhz f sclk v ddext = 2.5 v, v ddint < tbd v tbd mhz 208 mbga f sclk v ddext = 3.3 v, v ddint >= tbd v tbd mhz f sclk v ddext = 3.3 v, v ddint < tbd v tbd mhz f sclk v ddext = 2.5 v, v ddint >= tbd v tbd mhz f sclk v ddext = 2.5 v, v ddint < tbd v tbd mhz
rev. pre | page 24 of 60 | july 2005 adsp-bf534 preliminary technical data table 14. clock input and reset timing parameter minimum maximum unit timing requirement s t ckin clkin period 1 20.0 100.0 ns t ckinl clkin low pulse 2 10.0 ns t ckinh clkin high pulse 2 10.0 ns t bufdlay clkin to clkbuf delay tbd ns t wrst reset asserted pulsewidth low 3 11 t ckin ns 1 combinations of the clkin frequency and the pl l clock multiplier must no t exceed the allowed f vco , f cclk , and f sclk settings discussed in table 10 and table 11 . since by default the pll is multiplying the clkin fr equency by 10, 400mhz speed grade parts can not use the full clkin period range. 2 applies to bypass mode and non-bypass mode. 3 applies after power-up sequence is complete . at power-up, the processor s internal phase-locked loop requires no more than 2000 clkin cycles, while reset is asserted, assuming stable power supplies and clkin (not incl uding start-up time of external clock oscillator). figure 9. clock and reset timing reset clkin t ckinh t ckin t ckinl t wrst clkbuf t bufdlay t bufdlay
adsp-bf534 preliminary technical data rev. pre | page 25 of 60 | july 2005 asynchronous memory read cycle timing table 15. asynchronous memory read cycle timing parameter minimum maximum unit timing requirements t sdat data15C0 setup before clkout 2.1 ns t hdat data15C0 hold after clkout 0.8 ns t sardy ardy setup before clkout 4.0 ns t hardy ardy hold after clkout 0.0 ns switching characteristic t do output delay after clkout 1 1 output pins include ams3C0 , abe1C0 , addr19C1, aoe , are . 6.0 ns t ho output hold after clkout 1 0.8 ns figure 10. asynchronous memory read cycle timing t do t sdat clkout amsx abe1C0 t ho be, address read t hdat data15?0 aoe t do t sardy t hardy access extended 3cycles hold 1cycle are t hardy ardy addr19?1 setup 2cycles programmed read access 4cycles t ho t sardy
rev. pre | page 26 of 60 | july 2005 adsp-bf534 preliminary technical data asynchronous memory write cycle timing table 16. asynchronous memory write cycle timing parameter minimum maximum unit timing requirements t sardy ardy setup before clkout 4.0 ns t hardy ardy hold after clkout 0.0 ns switching characteristic t ddat data15C0 disable after clkout 6.0 ns t endat data15C0 enable after clkout 1.0 ns t do output delay after clkout 1 1 output pins include ams3C0 , abe1C0 , addr19C1, data15C0, aoe, awe . 6.0 ns t ho output hold after clkout 1 0.8 ns figure 11. asynchronous memory write cycle timing t do t endat clkout amsx abe1?0 be, address t ho write data t ddat data15?0 awe t sardy t hardy setup 2cycles programmed write access 2 cycles access extended 1cycle hold 1cycle ardy addr19?1 t ho t sardy t do
adsp-bf534 preliminary technical data rev. pre | page 27 of 60 | july 2005 sdram interface timing table 17. sdram interface timing (vdd int =1.2 v) parameter minimum maximum unit timing requirement t ssdat data setup before clkout 2.1 ns t hsdat data hold after clkout 0.8 ns switching characteristic t sclk clkout period 1 1 the t sclk value is the inverse of the f sclk specification discussed in table 13 . package type and reduced supply voltages affe ct the best-case value of 7.5ns listed here. 7.5 ns t sclkh clkout width high 2.5 ns t sclkl clkout width low 2.5 ns t dcad command, addr, data delay after clkout 2 2 command pins include: sras , scas , swe , sdqm, sms , sa10, scke. 6.0 ns t hcad command, addr, data hold after clkout 2 0.8 ns t dsdat data disable after clkout 6.0 ns t ensdat data enable after clkout 1.0 ns figure 12. sdram interface timing t hcad t hcad t dsdat t dcad t ssdat t dcad t ensdat t hsdat t sclkl t sclkh t sclk clkout data (in) data(out) cmnd addr (out) note: command = sras , scas , swe ,sdqm, sms , sa10, scke.
rev. pre | page 28 of 60 | july 2005 adsp-bf534 preliminary technical data external port bus request and grant cycle timing table 18 and figure 13 describe external port bus request and bus grant operations. table 18. external port bus request and grant cycle timing parameter 1, 2 minimum maximum unit timing requirements t bs br asserted to clkout high setup 4.6 ns t bh clkout high to br de-asserted hold time 0.0 ns switching characteristics t sd clkout low to xms , address, and rd /wr disable 4.5 ns t se clkout low to xms , address, and rd /wr enable 4.5 ns t dbg clkout high to bg asserted setup 3.6 ns t ebg clkout high to bg de-asserted hold time 3.6 ns t dbh clkout high to bgh asserted setup 3.6 ns t ebh clkout high to bgh de-asserted hold time 3.6 ns 1 these are preliminary timing parameters that ar e based on worst-case operating conditions. 2 the pad loads for these timing parameters are 20 pf. figure 13. external port bus request and grant cycle timing t bh addr19-1 amsx clkout t bs t sd t sd t sd t dbg t dbh t se t se t se t ebg t ebh bg awe bgh are br abe1-0
adsp-bf534 preliminary technical data rev. pre | page 29 of 60 | july 2005 external dma request timing table 19 and figure 14 describe the external dma request operations. table 19. external dma request timing parameter minimum maximum unit timing parameters t dr dmarx asserted to clkout high setup tbd tbd ns t dh clkout high to dmarx de-asserted hold time tbd tbd ns switching characteristics t do output delay after clkout 1 tbd tbd ns t ho output hold after clkout 1 tbd tbd ns 1 system outputs=data15C0, addr19C1, abe1C0 , aoe , are , awe , ams3C0 , sras , scas , swe , scke, clkout, sa10, sms , scl, sda, tsclk0, tfs0, rfs0, rsclk0, dt0pri, dt0sec, pf15C0, pg15C0, ph15C0, rtx0, td0, emu , xtal, vrout. figure 14. external dma request timing amsx clkout t dr t ho dmar0/1 t do t dh
rev. pre | page 30 of 60 | july 2005 adsp-bf534 preliminary technical data parallel peripheral interface timing table 20 and figure 15 on page 30 , figure 16 on page 33 , and figure 17 on page 34 describe parallel peripheral interface operations. table 20. parallel peripheral interface timing parameter minimum maximum unit timing requirements t pclkw ppi_clk width 1 6.0 ns t pclk ppi_clk period 1 15.0 ns timing requirements - gp in put and frame capture modes t sfspe external frame sync setup before ppi_clk 3.0 ns t hfspe external frame sync hold after ppi_clk 3.0 ns t sdrpe receive data setup before ppi_clk 2.0 ns t hdrpe receive data hold after ppi_clk 4.0 ns switching characteristics - gp output and frame capture modes t dfspe internal frame sync delay after ppi_clk 10.0 ns t hofspe internal frame sync hold after ppi_clk 0.0 ns t ddtpe transmit data delay after ppi_clk 10.0 ns t hdtpe transmit data hold after ppi_clk 0.0 ns 1 ppi_clk frequency cannot exceed f sclk /2 figure 15. parallel peripheral interface timing t ddtpe t hdtpe ppi_clk ppi_fs1 ppix drive edge sample edge t sfspe t hfspe t pclkw t dfspe t hofspe ppi_fs2 t sdrpe t hdrpe
adsp-bf534 preliminary technical data rev. pre | page 31 of 60 | july 2005 serial ports table 21 through table 26 on page 32 and figure 16 on page 33 through figure 18 on page 35 describe serial port operations. table 21. serial portsexternal clock parameter minimum maximum unit timing requirements t sfse tfs/rfs setup before tsclk/rsclk 1 3.0 ns t hfse tfs/rfs hold after tsclk/rsclk 1 3.0 ns t sdre receive data setup before rsclk 1 3.0 ns t hdre receive data hold after rsclk 1 3.0 ns t sclkew tsclk/rsclk width 4.5 ns t sclke tsclk/rsclk period 15.0 ns 1 referenced to sample edge. table 22. serial portsinternal clock parameter minimum maximum unit timing requirements t sfsi tfs/rfs setup before tsclk/rsclk 1 8.0 ns t hfsi tfs/rfs hold after tsclk/rsclk 1 C2.0 ns t sdri receive data setup before rsclk 1 6.0 ns t hdri receive data hold after rsclk 1 0.0 ns t sclkew tsclk/rsclk width 4.5 ns t sclke tsclk/rsclk period 15.0 ns 1 referenced to sample edge. table 23. serial portsexternal clock parameter minimum maximum unit switching characteristics t dfse tfs/rfs delay after tsclk/rsclk (internally generated tfs/rfs) 1 10.0 ns t hofse tfs/rfs hold after tsclk/rsclk (internally generated tfs/rfs) 1 0.0 ns t ddte transmit data delay after tsclk 1 10.0 ns t hdte transmit data hold after tsclk 1 0.0 ns 1 referenced to drive edge. table 24. serial portsinternal clock parameter minimum maximum unit switching characteristics t dfs i tfs/rfs delay after tsclk/rsclk (internally generated tfs/rfs) 1 3.0 ns t hofs i tfs/rfs hold after tsclk/rsclk (internally generated tfs/rfs) 1 ? 1.0 ns t ddt i transmit data delay after tsclk 1 3.0 ns t hdt i transmit data hold after tsclk 1 ? 2.0 ns t sclkiw tsclk/rsclk width 4.5 ns 1 referenced to drive edge.
rev. pre | page 32 of 60 | july 2005 adsp-bf534 preliminary technical data table 25. serial portsenable and three-state parameter minimum maximum unit switching characteristics t dtene data enable delay from external tsclk 1 0.0 ns t ddtte data disable delay from external tsclk 1 10.0 ns t dteni data enable delay from internal tsclk 1 C2.0 ns t ddtti data disable delay from internal tsclk 1 3.0 ns 1 referenced to drive edge. table 26. external late frame sync parameter minimum maximum unit switching characteristics t ddtlfse data delay from late external tfs or external rfs with mce = 1, mfd = 0 1,2 10.0 ns t dtenlfse data enable from late fs or mce = 1, mfd = 0 1,2 0.0 ns 1 mce = 1, tfs enable and tfs valid follow t ddtenfs and t ddtlfse . 2 if external rfs/tfs setup to rsclk/tsclk > t sclke /2 then t ddtlsck and t dtenlsck apply, otherwise t ddtlfse and t dtenlfs apply.
adsp-bf534 preliminary technical data rev. pre | page 33 of 60 | july 2005 figure 16. serial ports dt dt t ddtte t ddtene t ddtti t ddteni drive edge drive edge drive edge drive edge tsclk / rsclk tsclk / rsclk tsclk (ext) tfs ("late", ext.) tsclk (int) tfs ("late", int.) t sdri rsclk rfs dr drive edge sample edge t hdri t sfsi t hfsi t dfse t hofse t sclkiw data receive- internal clock t sdre data receive- external clock rsclk rfs dr drive edge sample edge t hdre t sfse t hfse t dfse t sclkew t hofse note: either the rising edge or falling edge of rclk, tclk can be used as the active sampling edge. t ddti t hdti tsclk tfs dt drive edge sample edge t sfsi t hfsi t sclkiw t dfsi t hofsi data transmit- internal clock t ddte t hdte tsclk tfs dt drive edge sample edge t sfse t hfse t dfse t sclkew t hofse data transmit- external clock note: either the rising edge or falling edge of rclk or tclk can be used as the active sampling edge.
rev. pre | page 34 of 60 | july 2005 adsp-bf534 preliminary technical data figure 17. external late frame sync (frame sync setup < t sclke /2) t ddtlfse t sfse/i t hdte/i rsclk drive drive sample rfs dt 2nd bit 1st bit t dtenlfse t ddte/i t hofse/i t dtenlfse t sfse/i t hdte/i drive drive sample dt tsclk tfs 2nd bit 1st bit t ddtlfse t ddte/i t hofse/i external rfs with mce = 1, mfd = 0 late external tfs
adsp-bf534 preliminary technical data rev. pre | page 35 of 60 | july 2005 figure 18. external late frame sync (frame sync setup > t sclke /2) dt rsclk rfs t sfse/i t hofse/i t dtenlsck t ddte/i t hdte/i t ddtlsck drive sample 1st bit 2nd bit drive dt tsclk tfs t sfse/i t hofse/i t dtenlsck t ddte/i t hdte/i t ddtlsck drive sample 1st bit 2nd bit drive late external tfs external rfs with mce=1, mfd=0
rev. pre | page 36 of 60 | july 2005 adsp-bf534 preliminary technical data serial peripheral interface (spi) portmaster timing table 27 and figure 19 describe spi port master operations. table 27. serial peripheral interface (spi) portmaster timing parameter minimum maximum unit timing requirements t sspidm data input valid to sck edge (data input setup) 7.5 ns t hspidm sck sampling edge to data input invalid C1.5 ns switching characteristics t sdscim spiselx low to first sck edge (x=0 or 1) 2t sclk C1.5 ns t spichm serial clock high period 2t sclk C1.5 ns t spiclm serial clock low period 2t sclk C1.5 ns t spiclk serial clock period 4t sclk C1.5 ns t hdsm last sck edge to spiselx high (x=0 or 1) 2t sclk C1.5 ns t spitdm sequential transfer delay 2t sclk C1.5 ns t ddspidm sck edge to data out valid (data out delay) 0 6 ns t hdspidm sck edge to data out invalid (data out hold) C1.0 4.0 ns figure 19. serial peripheral interface (spi) portmaster timing t sspidm t hspidm t hdspidm lsb msb t hspidm t ddspidm mosi (output) miso (input) spiselx (output) sck (cpol = 0) (output) sck (cpol = 1) (output) t spichm t spiclm t spiclm t spiclk t spichm t hdsm t spitdm t hdspidm lsb valid lsb msb msb valid t hspidm t ddspidm mosi (output) miso (input) t sspidm cpha=1 cpha=0 msb valid t sdscim t sspidm lsb valid
adsp-bf534 preliminary technical data rev. pre | page 37 of 60 | july 2005 serial peripheral interface (spi) portslave timing table 28 and figure 20 describe spi port slave operations. table 28. serial peripheral interface (spi) portslave timing parameter minimum maximum unit timing requirements t spichs serial clock high period 2t sclk C1.5 ns t spicls serial clock low period 2t sclk C1.5 ns t spiclk serial clock period 4t sclk C1.5 ns t hds last sck edge to spiss not asserted 2t sclk C1.5 ns t spitds sequential transfer delay 2t sclk C1.5 ns t sdsci spiss assertion to first sck edge 2t sclk C1.5 ns t sspid data input valid to sck edge (data input setup) 1.6 ns t hspid sck sampling edge to data input invalid 1.6 ns switching characteristics t dsoe spiss assertion to data out active 0 8 ns t dsdhi spiss deassertion to data high impedance 0 8 ns t ddspid sck edge to data out valid (data out delay) 0 10 ns t hdspid sck edge to data out invalid (data out hold) 0 10 ns figure 20. serial peripheral interface (spi) portslave timing t hspid t ddspid t dsdhi lsb msb msb valid t hspid t dsoe t ddspid t hdspid miso (output) mosi (input) t sspid spiss (input) sck (cpol = 0) (input) sck (cpol = 1) (input) t sdsci t spichs t spicls t spicls t spiclk t hds t spichs t sspid t hspid t dsdhi lsb valid msb msb valid t dsoe t ddspid miso (output) mosi (input) t sspid lsb valid lsb cpha=1 cpha=0 t spitds
rev. pre | page 38 of 60 | july 2005 adsp-bf534 preliminary technical data universal asynchronous receiver-transmitter (uart) portsreceive and transmit timing figure 21 describes the uart ports receive and transmit opera- tions. the maximum baud rate is sclk/16. as shown in figure 21 there is some latency between the generation of internal uart interrupts and the external data operations. these latencies are negligible at the data transmission rates for the uart. figure 21. uart portsrece ive and transmit timing uartx rx data(5?8) internal uart receive interrupt uart receive bit set by data stop; cleared by fifo read clkout (sample clock) uartx tx data(5?8) stop (1?2) internal uart transmit interrupt uart transmit bit set by program; cleared by write to transmit start stop transmit receive
adsp-bf534 preliminary technical data rev. pre | page 39 of 60 | july 2005 general-purpose port timing table 29 and figure 22 describe general-purpose port operations. table 29. general-purpose port timing parameter minimum maximum unit timing requirement t wfi general-purpose port pin input pulsewidth t sclk + 1 ns t gppis general-purpose port pin input setup tbd ns t gppih general-purpose port pin input hold tbd ns switching characteristic t gpod general-purpose port pin output delay from clkout low 0 6 ns figure 22. general-purpose port timing gpp input gpp output clkout t gpod t gppis t gppih t wfi
rev. pre | page 40 of 60 | july 2005 adsp-bf534 preliminary technical data timer cycle timing table 30 and figure 23 describe timer expired operations. the input signal is asynchronous in width capture mode and external clock mode and has an absolute maximum input fre- quency of f sclk /2 mhz. table 30. timer cycle timing parameter minimum maximum unit timing characteristics t wl timer pulsewidth input low 1 (measured in sclk cycles) 1 sclk t wh timer pulsewidth input high 1 (measured in sclk cycles) 1 sclk t tis timer input setup time before clkout low tbd ns t tih timer input hold time after clkout low tbd ns switching characteristic t hto timer pulsewidth output 2 (measured in sclk cycles) 1 (2 32 C1) sclk t tod timer output update delay after clkout low 0 tbd ns 1 the minimum pulsewidths apply for tm rx signals in width capture an d external clock modes. they al so apply to the pf15 or ppi_cl k signals in pwm output mode. 2 the minimum time for t hto is one cycle, and the maximum time for t hto equals (2 32 C1) cycles. figure 23. timer cycle timing timer input timer output clkout t tod t tis t tih
adsp-bf534 preliminary technical data rev. pre | page 41 of 60 | july 2005 jtag test and emulation port timing table 31 and figure 24 describe jtag port operations. table 31. jtag port timing parameter minimum maximum unit timing parameters t tck tck period 20 ns t stap tdi, tms setup before tck high 4 ns t htap tdi, tms hold after tck high 4 ns t ssys system inputs setup before tck high 1 4ns t hsys system inputs hold after tck high 1 5ns t trstw trst pulsewidth 2 (measured in tck cycles) 4 tck switching characteristics t dtdo tdo delay from tck low 10 ns t dsys system outputs delay after tck low 3 012ns 1 system inputs=data15C0, br , ardy, scl, sda, tfs0, tsclk0, rsclk0, rfs0, dr0pri, dr 0sec, pf15C0, pg15C0, ph15C0, rtxi, tck, td1, tms, trst , clkin, reset , nmi , bmode2C0. 2 50 mhz maximum 3 system outputs=data15C0, addr19C1, abe1C0 , aoe , are , awe , ams3C0 , sras , scas , swe , scke, clkout, sa10, sms , scl, sda, tsclk0, tfs0, rfs0, rsclk0, dt0pri, dt0sec, pf15C0, pg15C0, ph15C0, rtx0, td0, emu , xtal, vrout. figure 24. jtag port timing tms tdi tdo system inputs system outputs tck t tck t htap t stap t dtdo t ssys t hsys t dsys
rev. pre | page 42 of 60 | july 2005 adsp-bf534 preliminary technical data twi controller timing table 32 through table 39 and figure 25 through figure 28 describe the twi controller operations. table 32. twi controller timing: bus st art/stop bits, slave mode, 100 khz parameter minimum maximum unit t su:sta start condition setup time tbd - ns t hd:sta start condition hold time tbd - ns t su:sto stop condition setup time tbd - ns t hd:sto stop condition hold time tbd - ns table 33. twi controller timing: bus st art/stop bits, slave mode, 400 khz parameter minimum maximum unit t su:sta start condition setup time tbd - ns t hd:sta start condition hold time tbd - ns t su:sto stop condition setup time tbd - ns t hd:sto stop condition hold time tbd - ns table 34. twi controller timing: bus da ta requirements, slave mode, 100 khz parameter minimum maximum unit t high clock high time tbd - s t low clock low time tbd - s t r sda and scl rise time - tbd ns t f sda and scl fall time - tbd ns t su:sta start condition setup time tbd - s t hd:sta start condition hold time tbd - s t hd:dat data input hold time tbd - ns t su:dat data input setup time 1 tbd - ns t su:sto stop condition setup time tbd - s t taa output valid from clock 2 -tbdns t buf bus free time tbd - s c b bus capacitive loading - tbd pf 1 as a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. tbd ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2 a fast mode twi bus device can be used in a st andard mode twi bus system, but the requirement t su:dat >= 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, i t must output the next data bit to the sda line. before the scl line is released, t r max. + t su:dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification).
adsp-bf534 preliminary technical data rev. pre | page 43 of 60 | july 2005 table 35. twi controller timing: bus da ta requirements, slave mode, 400 khz parameter minimum maximum unit t high clock high time tbd - s t low clock low time tbd - s t r sda and scl rise time tbd tbd ns t f sda and scl fall time tbd tbd ns t su:sta start condition setup time tbd - s t hd:sta start condition hold time tbd - s t hd:dat data input hold time tbd tbd s t su:dat data input setup time 1 tbd - ns t su:sto stop condition setup time tbd - s t taa output valid from clock - - ns t buf bus free time tbd - s c b bus capacitive loading - tbd pf 1 as a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. tbd ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. table 36. twi controller timing: bus st art/stop bits, master mode, 100 khz parameter minimum maximum unit t su:sta start condition setup time tbd - ns t hd:sta start condition hold time tbd - ns t su:sto stop condition setup time tbd - ns t hd:sto stop condition hold time tbd - ns table 37. twi controller timing: bus st art/stop bits, master mode, 400 khz parameter minimum maximum unit t su:sta start condition setup time tbd - ns t hd:sta start condition hold time tbd - ns t su:sto stop condition setup time tbd - ns t hd:sto stop condition hold time tbd - ns table 38. twi controller timing: bus data requirements, master mode, 100 khz parameter minimum maximum unit t high clock high time tbd - ms t low clock low time tbd - ms t r sda and scl rise time - tbd ns t f sda and scl fall time - tbd ns t su:sta start condition setup time tbd - ms t hd:sta start condition hold time tbd - ms t hd:dat data input hold time tbd - ns t su:dat data input setup time 1 tbd - ns t su:sto stop condition setup time tbd - ms t taa output valid from clock - tbd ns t buf bus free time tbd - ms c b bus capacitive loading - tbd pf 1 a fast mode twi bus device can be used in a st andard mode twi bus system, but the requirement t su:dat >= 250 ns must then be met. this will automatically be the case if the device does not stretch the l ow period of the scl signal. if such a device do es stretch the low period of the scl signal, i t must output the next data bit to the sda line. before the scl line is released, t r max. + t su:dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification).
rev. pre | page 44 of 60 | july 2005 adsp-bf534 preliminary technical data table 39. twi controller timing: bus data requirements, master mode, 400 khz parameter minimum maximum unit t high clock high time tbd - ms t low clock low time tbd - ms t r sda and scl rise time tbd tbd ns t f sda and scl fall time tbd tbd ns t su:sta start condition setup time tbd - ms t hd:sta start condition hold time tbd - ms t hd:dat data input hold time tbd tbd ns t su:dat data input setup time 1 tbd - ns t su:sto stop condition setup time tbd - ms t taa output valid from clock - - ns t buf bus free time tbd - ms c b bus capacitive loading - tbd pf 1 a fast mode twi bus device can be used in a st andard mode twi bus system, but the requirement t su:dat >= 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, i t must output the next data bit to the sda line. before the scl line is released, t r max. + t su:dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification). figure 25. twi controller timing : bus start/stop bits, slave mode figure 26. twi controller ti ming: bus data, slave mode scl t su:sta t hd:sta sda start stop t su:sto t hd:sto scl t su :s ta t high t f sda (out) sda (i n) t hd:sta t aa t lo w t hd:dat t su:dat t r t su:sto t aa t buf
adsp-bf534 preliminary technical data rev. pre | page 45 of 60 | july 2005 figure 27. twi controller timing: bus start/stop bi ts, master mode figure 28. twi controller ti ming: bus data, master mode scl t su:sta t hd:sta sda start stop t su:sto t hd:sto scl t su :s ta t high t f sda (out) sda (i n) t hd:sta t aa t lo w t hd:dat t su:dat t r t su:sto t aa t buf
rev. pre | page 46 of 60 | july 2005 adsp-bf534 preliminary technical data output drive currents figure 29 through figure 38 show typical current-voltage char- acteristics for the output driver s of the adsp-bf534 processor. the curves represent the current drive capability of the output drivers as a function of output voltage. see table 9 on page 17 for information about which driver type corresponds to a par- ticular pin. figure 29. drive current a (low v ddext ) figure 30. drive current a (high v ddext ) source current (ma) source voltage (v) 150 100 50 0 ?50 ?100 ?150 0 0.5 1.0 1.5 2.0 2.5 3.0 tbd source current (ma) source voltage (v) 150 100 50 0 ?50 ?100 ?150 0 0.5 1.0 1.5 2.0 2.5 3.0 tbd figure 31. drive current b (low v ddext ) figure 32. drive current b (high v ddext ) source current (ma) source voltage (v) 150 100 50 0 ?50 ?100 ?150 0 0.5 1.0 1.5 2.0 2.5 3.0 tbd source current (ma) source voltage (v) 150 100 50 0 ?50 ?100 ?150 0 0.5 1.0 1.5 2.0 2.5 3.0 tbd
adsp-bf534 preliminary technical data rev. pre | page 47 of 60 | july 2005 figure 33. drive current c (low v ddext ) figure 34. drive current c (high v ddext ) source current (ma) source voltage (v) 150 100 50 0 ?50 ?100 ?150 0 0.5 1.0 1.5 2.0 2.5 3.0 tbd source current (ma) source voltage (v) 150 100 50 0 ?50 ?100 ?150 0 0.5 1.0 1.5 2.0 2.5 3.0 tbd figure 35. drive current d (low v ddext ) figure 36. drive current d (high v ddext ) source current (ma) source voltage (v) 150 100 50 0 ?50 ?100 ?150 0 0.5 1.0 1.5 2.0 2.5 3.0 tbd source current (ma) source voltage (v) 150 100 50 0 ?50 ?100 ?150 0 0.5 1.0 1.5 2.0 2.5 3.0 tbd
rev. pre | page 48 of 60 | july 2005 adsp-bf534 preliminary technical data figure 37. drive current e (low v ddext ) figure 38. drive current e (high v ddext ) source current (ma) source voltage (v) 150 100 50 0 ?50 ?100 ?150 0 0.5 1.0 1.5 2.0 2.5 3.0 tbd source current (ma) source voltage (v) 150 100 50 0 ?50 ?100 ?150 0 0.5 1.0 1.5 2.0 2.5 3.0 tbd
adsp-bf534 preliminary technical data rev. pre | page 49 of 60 | july 2005 power dissipation total power dissipation has two components: one due to inter- nal circuitry (p int ) and one due to the sw itching of external output drivers (p ext ). table 40 shows the power dissipation for internal circuitry (v ddint ). internal power di ssipation is depen- dent on the instruction execution sequence and the data operands involved. the external component of total power dissipation is caused by the switching of output pins. its magnitude depends on: ? maximum frequency (f 0 ) at which all output pins can switch during each cycle ? load capacitance (c 0 ) of all switching output pins ? their voltage swing (v ddext ) the external component is calculated using: the frequency f includ es driving the load high and then back low. for example: data15C0 pins can drive high and low at a maximum rate of 1/(2 t sclk ) while in sdram burst mode. a typical power consum ption can now be calculated for these conditions by adding a typical internal power dissipation: note that the conditions causing a worst-case p ext differ from those causing a worst-case p int . maximum p int cannot occur while 100% of the output pins are switching from all ones (1s) to all zeros (0s). note, as well, that it is not common for an applica- tion to have 100% or even 50% of the outputs switching simultaneously. test conditions all timing parameters appearing in this data sheet were mea- sured under the conditions described in this section. output enable time output pins are considered to be enabled when th ey have made a transition from a high impedanc e state to the po int when they start driving. the output enable time t ena is the interval from the point when a reference signal reaches a high or low voltage level to the point when the output starts driving as shown in the output enable/disable diagram ( figure 39 ). the time t ena_measured is the interval from wh en the reference signal switches to when the output voltage reaches 2.0 v (output high) or 1.0 v (output low). time t trip is the interval from when the output starts driving to when the output reaches the 1.0 v or 2.0 v trip voltage. time t ena is calculated as shown in the equation: if multiple pins (such as the data bus) are enabled, the measure- ment value is that of the first pin to start driving. table 40. internal power dissipation test conditions 1 1 i dd data is specified for typical proc ess parameters. all data at 25oc. parameter f cclk = 50 mhz v ddint = 0.8 v f cclk = 150 mhz v ddint = 0.9 v f cclk = 250 mhz v ddint = 1.0 v f cclk = 400 mhz v ddint = 1.2 v unit i ddtyp 2 2 processor executing 75% dual mac, 25% add wi th moderate data bus activity. tbdtbdtbdtbdma i ddefr 3 3 implementation of enhanced full rate (efr) gsm algorithm. tbdtbdtbdtbdma i ddsleep 45 4 see the adsp-bf537 blackfin processor hardware reference manual for defini- tions of sleep and deep sleep operating modes. 5 i ddhibernate is measured @ v ddext = 3.65 v with vr off (v ddcore =0v). tbdtbdtbdtbdma i dddeepsleep 4 tbdtbdtbdtbdma i ddhibernate 5 50 50 50 50 a parameter f cclk = 200 mhz v ddint = 0.9 v f cclk = 400 mhz v ddint = 1.0 v f cclk = 500 mhz v ddint = 1.2 v unit i ddtyp 2 - tbd tbd tbd ma i ddefr 3 - tbd tbd tbd ma i ddsleep 45 - tbd tbd tbd ma i dddeepsleep 4 - tbd tbd tbd ma i ddhibernate 5 -505050 a p ext v ddext 2 c 0 f 0 ? = p total p ext i dd v ddint () + = t ena t ena_measured t trip ? =
rev. pre | page 50 of 60 | july 2005 adsp-bf534 preliminary technical data output disable time output pins are considered to be disabled when they stop driv- ing, go into a high impedance stat e, and start to decay from their output high or low voltage. the time for the voltage on the bus to decay by ? v is dependent on the capacitive load, c l and the load current, i l . this decay time can be approximated by the equation: the output disable time t dis is the difference between t dis_measured and t decay as shown in figure 39 . the time t dis_measured is the interval from when the reference signal switches to when the output voltage decays ? v from the mea- sured output high or output low voltage. the time t decay is calculated with test loads c l and i l , and with ? v equal to 0.5 v. example system hold time calculation to determine the data output hold time in a particular system, first calculate t decay using the equation given above. choose ? v to be the difference between the adsp-bf534 processors out- put voltage and the input threshol d for the device requiring the hold time. a typical ? v will be 0.4 v. c l is the total bus capaci- tance (per data line), and i l is the total leakage or three-state current (per data line). the hold time will be t decay plus the minimum disable time (for example, t dsdat for an sdram write cycle). figure 39. output enable/disable t decay c l v ? () i l ? = reference signal t dis output starts driving v oh (measured) v v ol (measured) + v t dis_measured v oh (measured) v ol (measured) 2.0v 1.0v v oh (measured) v ol (measured) high impedance state. test conditions cause this voltage to be approximately 1.5v. output stops driving t ena t decay t ena-measured t trip figure 40. equivalent device loading for ac measurements (includes all fixtures) figure 41. voltage refe rence levels for ac measurements (except output enable/disable) 1.5v 30pf to output pin 50 v input or output 1.5v 1.5v
adsp-bf534 preliminary technical data rev. pre | page 51 of 60 | july 2005 environmental conditions to determine the junction te mperature on the application printed circuit board use: where: t j = junction temperature ( c) t case = case temperature ( c) measured by customer at top center of package. jt = from table 41 p d = power dissipation (see power dissipation on page 49 for the method to calculate p d ) values of ja are provided for package comparison and printed circuit board design considerations. ja can be used for a first order approximation of t j by the equation: where: t a = ambient temperature ( c) values of jc are provided for packag e comparison and printed circuit board design considerations when an external heatsink is required. values of jb are provided for package comparison and printed circuit board design considerations. in table 41 , airflow measurements comply with jedec stan- dards jesd51-2 and jesd51-6, and the junction-to-board measurement complies with je sd51-8. the junction-to-case measurement complies with mil-std-883 (method 1012.1). all measurements use a 2s2p jedec test board. table 41. thermal characteristics parameter condition typical unit ja 0 linear m/s air flow c/w jma 1 linear m/s air flow c/w jma 2 linear m/s air flow c/w jb c/w jc c/w jt 0 linear m/s air flow c/w t j t case jt p d () + = t j t a ja p d () + =
rev. pre | page 52 of 60 | july 2005 adsp-bf534 preliminary technical data 182-ball mini-bga pinout table 42 lists the mini-bga pino ut by signal mnemonic. table 43 on page 53 lists the mini-bga pinout by ball number. table 42. 182-ball mini-bga ball assignment (alphabetically by signal mnemonic) mnemonic ball no. mnemonic ball no. mnemonic ball no. mnemonic ball no. mnemonic ball no. abe0 h13 clkout b14 gnd l6 pg8 e3 sras d13 abe1 h12 data0 m9 gnd l8 pg9 e4 swe d12 addr1 j14 data1 n9 gnd l10 ph0 c2 tck p2 addr10 m13 data10 n6 gnd m4 ph1 c3 tdi m3 addr11 m14 data11 p6 gnd m10 ph10 b6 tdo n3 addr12 n14 data12 m5 gnd p14 ph11 a2 tms n2 addr13 n13 data13 n5 nmi b10 ph12 a3 trst n1 addr14 n12 data14 p5 pf0 m1 ph13 a4 vddext a1 addr15 m11 data15 p4 pf1 l1 ph14 a5 vddext c12 addr16 n11 data2 p9 pf10 j2 ph15 a6 vddext e6 addr17 p13 data3 m8 pf11 j3 ph2 c4 vddext e11 addr18 p12 data4 n8 pf12 h1 ph3 c5 vddext f4 addr19 p11 data5 p8 pf13 h2 ph4 c6 vddext f12 addr2 k14 data6 m7 pf14 h3 ph5 b1 vddext h5 addr3 l14 data7 n7 pf15 h4 ph6 b2 vddext h10 addr4 j13 data8 p7 pf2 l2 ph7 b3 vddext j11 addr5 k13 data9 m6 pf3 l3 ph8 b4 vddext j12 addr6 l13 emu m2 pf4 l4 ph9 b5 vddext k7 addr7 k12 gnd a10 pf5 k1 pj0 c7 vddext k9 addr8 l12 gnd a14 pf6 k2 pj1 b7 vddext l7 addr9 m12 gnd d4 pf7 k3 pj10 d10 vddext l9 ams0 e14 gnd e7 pf8 k4 pj11 d11 vddext l11 ams1 f14 gnd e9 pf9 j1 pj2 b11 vddext p1 ams2 f13 gnd f5 pg0 g1 pj3 c11 vddint e5 ams3 g12 gnd f6 pg1 g2 pj4 d7 vddint e8 aoe g13 gnd f10 pg10 d1 pj5 d8 vddint e10 ardy e13 gnd f11 pg11 d2 pj6 c8 vddint g10 are g14 gnd g4 pg12 d3 pj7 b8 vddint k5 awe h14 gnd g5 pg13 d5 pj8 d9 vddint k8 bg p10 gnd g11 pg14 d6 pj9 c9 vddint k10 bgh n10 gnd h11 pg15 c1 reset c10 vddrtc b9 bmode0 n4 gnd j4 pg2 g3 rtxo a8 vrout0 a13 bmode1 p3 gnd j5 pg3 f1 rtxi a9 vrout1 b12 bmode2 l5 gnd j9 pg4 f2 sa10 e12 xtal a11 br d14 gnd j10 pg5 f3 scas c14 clkbuf a7 gnd k6 pg6 e1 scke b13 clkin a12 gnd k11 pg7 e2 sms c13
adsp-bf534 preliminary technical data rev. pre | page 53 of 60 | july 2005 table 43 lists the mini-bga pinout by ball number. table 42 on page 52 lists the mini-bga pino ut by signal mnemonic. table 43. 182-ball mini-bga ball assign ment (numerically by ball number) ball no. mnemonic ball no. mnemonic ball no. mnemonic ball no. mnemonic ball no. mnemonic a1 vddext c10 reset f5 gnd j14 addr1 m9 data0 a2 ph11 c11 pj3 f6 gnd k1 pf5 m10 gnd a3 ph12 c12 vddext f10 gnd k2 pf6 m11 addr15 a4 ph13 c13 sms f11 gnd k3 pf7 m12 addr9 a5 ph14 c14 scas f12 vddext k4 pf8 m13 addr10 a6 ph15 d1 pg10 f13 ams2 k5 vddint m14 addr11 a7 clkbuf d2 pg11 f14 ams1 k6 gnd n1 trst a8 rtxo d3 pg12 g1 pg0 k7 vddext n2 tms a9 rtxi d4 gnd g2 pg1 k8 vddint n3 tdo a10 gnd d5 pg13 g3 pg2 k9 vddext n4 bmode0 a11 xtal d6 pg14 g4 gnd k10 vddint n5 data13 a12 clkin d7 pj4 g5 gnd k11 gnd n6 data10 a13 vrout0 d8 pj5 g10 vddint k12 addr7 n7 data7 a14 gnd d9 pj8 g11 gnd k13 addr5 n8 data4 b1 ph5 d10 pj10 g12 ams3 k14 addr2 n9 data1 b2 ph6 d11 pj11 g13 aoe l1 pf1 n10 bgh b3 ph7 d12 swe g14 are l2 pf2 n11 addr16 b4 ph8 d13 sras h1 pf12 l3 pf3 n12 addr14 b5 ph9 d14 br h2 pf13 l4 pf4 n13 addr13 b6 ph10 e1 pg6 h3 pf14 l5 bmode2 n14 addr12 b7 pj1 e2 pg7 h4 pf15 l6 gnd p1 vddext b8 pj7 e3 pg8 h5 vddext l7 vddext p2 tck b9 vddrtc e4 pg9 h10 vddext l8 gnd p3 bmode1 b10 nmi e5 vddint h11 gnd l9 vddext p4 data15 b11 pj2 e6 vddext h12 abe1 l10 gnd p5 data14 b12 vrout1 e7 gnd h13 abe0 l11 vddext p6 data11 b13 scke e8 vddint h14 awe l12 addr8 p7 data8 b14 clkout e9 gnd j1 pf9 l13 addr6 p8 data5 c1 pg15 e10 vddint j2 pf10 l14 addr3 p9 data2 c2 ph0 e11 vddext j3 pf11 m1 pf0 p10 bg c3 ph1 e12 sa10 j4 gnd m2 emu p11 addr19 c4 ph2 e13 ardy j5 gnd m3 tdi p12 addr18 c5 ph3 e14 ams0 j9 gnd m4 gnd p13 addr17 c6 ph4 f1 pg3 j10 gnd m5 data12 p14 gnd c7 pj0 f2 pg4 j11 vddext m6 data9 c8 pj6 f3 pg5 j12 vddext m7 data6 c9 pj9 f4 vddext j13 addr4 m8 data3
rev. pre | page 54 of 60 | july 2005 adsp-bf534 preliminary technical data figure 42 shows the top view of the mini-bga ball configura- tion. figure 43 shows the bottom view of the mini-bga ball configuration. figure 42. 182-ball mi ni-bga ball config uration (top view) figure 43. 182-ball mini-bga ball configuration (bottom view) a b c d e f g h j k l m n p 1234567891011121314 v ddint v ddext gnd i/o key: v rout v ddrtc nc a b c d e f g h j k l m n p 1 2 3 4 5 6 7 8 9 10 11 12 13 14 v ddint v ddext gnd i/o key: v rout v ddrtc nc
adsp-bf534 preliminary technical data rev. pre | page 55 of 60 | july 2005 208-ball sparse mini-bga pinout table 44 lists the sparse mini-bga pinout by signal mnemonic. table 45 on page 56 lists the sparse mini -bga pinout by ball number. table 44. 208-ball sparse mini-bga ball assign ment (alphabetically by signal mnemonic) mnemonic ball no. mnemonic ball no. mnemonic ball no. mnemonic ball no. mnemonic ball no. abe0 p19 data12 y4 gnd m13 pg6 e2 tdi v1 abe1 p20 data13 w4 gnd n9 pg7 d1 tdo y2 addr1 r19 data14 y3 gnd n10 pg8 d2 tms u2 addr10 w18 data15 w3 gnd n11 pg9 c1 trst u1 addr11 y18 data2 y9 gnd n12 ph0 b4 vddext g7 addr12 w17 data3 w9 gnd n13 ph1 a5 vddext g8 addr13 y17 data4 y8 gnd p11 ph10 b9 vddext g9 addr14 w16 data5 w8 gnd v2 ph11 a10 vddext g10 addr15 y16 data6 y7 gnd w2 ph12 b10 vddext h7 addr16 w15 data7 w7 gnd w19 ph13 a11 vddext h8 addr17 y15 data8 y6 gnd y1 ph14 b11 vddext j7 addr18 w14 data9 w6 gnd y13 ph15 a12 vddext j8 addr19 y14 emu t1 gnd y20 ph2 b5 vddext k7 addr2 t20 gnd a1 nmi c20 ph3 a6 vddext k8 addr3 t19 gnd a13 pf0 t2 ph4 b6 vddext l7 addr4 u20 gnd a20 pf1 r1 ph5 a7 vddext l8 addr5 u19 gnd b2 pf10 l2 ph6 b7 vddext m7 addr6 v20 gnd g11 pf11 k1 ph7 a8 vddext m8 addr7 v19 gnd h9 pf12 k2 ph8 b8 vddext n7 addr8 w20 gnd h10 pf13 j1 ph9 a9 vddext n8 addr9 y19 gnd h11 pf14 j2 pj0 b12 vddext p7 ams0 m20 gnd h12 pf15 h1 pj1 b13 vddext p8 ams1 m19 gnd h13 pf2 r2 pj10 b19 vddext p9 ams2 g20 gnd j9 pf3 p1 pj11 c19 vddext p10 ams3 g19 gnd j10 pf4 p2 pj2 d19 vddint g12 aoe n20 gnd j11 pf5 n1 pj3 e19 vddint g13 ardy j19 gnd j12 pf6 n2 pj4 b18 vddint g14 are n19 gnd j13 pf7 m1 pj5 a19 vddint h14 awe r20 gnd k9 pf8 m2 pj6 b15 vddint j14 bg y11gndk10pf9l1 pj7 b16vddintk14 bgh y12gndk11pg0h2 pj8 b17vddintl14 bmode0 w13 gnd k12 pg1 g1 pj9 b20 vddint m14 bmode1 w12 gnd k13 pg10 c2 reset d20 vddint n14 bmode2 w11 gnd l9 pg11 b1 rtxo a15 vddint p12 br f19 gnd l10 pg12 a2 rtxi a14 vddint p13 clkbuf b14 gnd l11 pg13 a3 sa10 l20 vddint p14 clkin a18 gnd l12 pg14 b3 scas k20 vddrtc a16 clkout h19 gnd l13 pg15 a4 scke h20 vrout0 e20 data0 y10 gnd m9 pg2 g2 sms j20 vrout1 f20 data1 w10 gnd m10 pg3 f1 sras k19 xtal a17 data10 y5 gnd m11 pg4 f2 swe l19 data11 w5 gnd m12 pg5 e1 tck w1
rev. pre | page 56 of 60 | july 2005 adsp-bf534 preliminary technical data table 45 lists the sparse mini-bga pinout by ball number. table 44 on page 55 lists the sparse mini-b ga pinout by signal mnemonic. table 45. 208-ball sparse mini-bga ball as signment (numerically by ball number) ball no. mnemonic ball no. mnemonic ball no. mnemonic ball no. mnemonic ball no. mnemonic a1 gnd c19 pj11 j9 gnd m19 ams1 w1 tck a2 pg12 c20 nmi j10 gnd m20 ams0 w2 gnd a3 pg13 d1 pg7 j11 gnd n1 pf5 w3 data15 a4 pg15 d2 pg8 j12 gnd n2 pf6 w4 data13 a5 ph1 d19 pj2 j13 gnd n7 vddext w5 data11 a6 ph3 d20 reset j14 vddint n8 vddext w6 data9 a7 ph5 e1 pg5 j19 ardy n9 gnd w7 data7 a8 ph7 e2 pg6 j20 sms n10 gnd w8 data5 a9 ph9 e19 pj3 k1 pf11 n11 gnd w9 data3 a10 ph11 e20 vrout0 k2 pf12 n12 gnd w10 data1 a11 ph13 f1 pg3 k7 vddext n13 gnd w11 bmode2 a12 ph15 f2 pg4 k8 vddext n14 vddint w12 bmode1 a13 gnd f19 br k9 gnd n19 are w13 bmode0 a14 rtxi f20 vrout1 k10 gnd n20 aoe w14 addr18 a15 rtxo g1 pg1 k11 gnd p1 pf3 w15 addr16 a16 vddrtc g2 pg2 k12 gnd p2 pf4 w16 addr14 a17 xtal g7 vddext k13 gnd p7 vddext w17 addr12 a18 clkin g8 vddext k14 vddint p8 vddext w18 addr10 a19 pj5 g9 vddext k19 sras p9 vddext w19 gnd a20 gnd g10 vddext k20 scas p10 vddext w20 addr8 b1 pg11 g11 gnd l1 pf9 p11 gnd y1 gnd b2 gnd g12 vddint l2 pf10 p12 vddint y2 tdo b3 pg14 g13 vddint l7 vddext p13 vddint y3 data14 b4 ph0 g14 vddint l8 vddext p14 vddint y4 data12 b5 ph2 g19 ams3 l9 gnd p19 abe0 y5 data10 b6 ph4 g20 ams2 l10 gnd p20 abe1 y6 data8 b7 ph6 h1 pf15 l11 gnd r1 pf1 y7 data6 b8 ph8 h2 pg0 l12 gnd r2 pf2 y8 data4 b9 ph10 h7 vddext l13 gnd r19 addr1 y9 data2 b10 ph12 h8 vddext l14 vddint r20 awe y10 data0 b11 ph14 h9 gnd l19 swe t1 emu y11 bg b12 pj0 h10 gnd l20 sa10 t2 pf0 y12 bgh b13 pj1 h11 gnd m1 pf7 t19 addr3 y13 gnd b14 clkbuf h12 gnd m2 pf8 t20 addr2 y14 addr19 b15 pj6 h13 gnd m7 vddext u1 trst y15 addr17 b16 pj7 h14 vddint m8 vddext u2 tms y16 addr15 b17 pj8 h19 clkout m9 gnd u19 addr5 y17 addr13 b18 pj4 h20 scke m10 gnd u20 addr4 y18 addr11 b19pj10j1 pf13m11gndv1 tdi y19addr9 b20 pj9 j2 pf14 m12 gnd v2 gnd y20 gnd c1 pg9 j7 vddext m13 gnd v19 addr7 c2 pg10 j8 vddext m14 vddint v20 addr6
adsp-bf534 preliminary technical data rev. pre | page 57 of 60 | july 2005 figure 44 shows the top view of the sparse mini-bga ball con- figuration. figure 45 shows the bottom view of the sparse mini- bga ball configuration. figure 44. 208-ball mi ni-bga ball config uration (top view) figure 45. 208-ball mini-bga ball configuration (bottom view) a b c d e f g h j k l m n p 1234567891011121314 1617181920 15 v ddint v ddext gnd i/o key: v rout v ddrtc r t u v w y nc a b c d e f g h j k l m n p 20 19 18 17 16 15 14 13 12 11 10 9 8 7 5 4 3 2 1 6 v ddint v ddext gnd i/o key: v rout v ddrtc r t u v w y nc
rev. pre | page 58 of 60 | july 2005 adsp-bf534 preliminary technical data outline dimensions dimensions in figure 46 182-ball mini-bga and figure 47 208-ball sparse mini-bga are shown in millimeters. figure 46. 182-ball mini-bga figure 47. 208-ba ll sparse mini-bga 0.80 bsc typ detail a detail a 0.50 0.45 0.40 1.31 1.21 1.10 10.40 bsc sq a b c d e f g h j k l m n p 14 13 12 11 10 8 7 6 3 2 1 95 4 a 1corner index area top view bottom view 1.70 1.56 1.35 12.00 bsc sq (ball diameter) seating plane 0.35 nom 0.25 min 0.12 coplanarity pin a1 indicator location notes: 1. dimensions are in millimeters. 2. compliant to jedec standard mo-205-ae, except for ball diameter. 3. center dimensions are nominal. 4. the actual position of the ball grid is within 0.15 of its ideal position relative to the package edges. 5. recommended solder mask opening is 0.40mm, recommended ball pad size is 0.55mm. 0.80 bsc typ a b c d e f g h j k l m n p r t u v w y 15 14 17 16 19 18 20 13 12 11 10 9 8 7 6 5 4 3 2 1 bottom view 15.20 bsc sq a 1 corner index area 0.12 coplanarity detail a 0.50 0.45 0.40 (ball diameter) 0.35 nom 0.30 min top view pin a1 indicator location detail a 17.00 bsc sq seating plane 1.70 1.61 1.46 1.36 1.26 1.16 notes: 1. dimensions are in millimeters. 2. compliant to jedec standard mo-205-am, except for ball diameter. 3. center dimensions are nominal. 4. the actual position of the ball grid is within 0.15 of its ideal position relative to the package edges. 5. recommended solder mask opening is 0.40mm, recommended ball pad size is 0.55mm.
adsp-bf534 preliminary technical data rev. pre | page 59 of 60 | july 2005 ordering guide part numbers that include a 1 are 182-ball mi ni-bga. part numbers that include b1 are 208-ball sparse mini-bga. part numbers that include z are lead free. see figure 8 on page 22 for more information about product information on the package. the adsp-bf534 processor is also available with a C40oc to 105oc ambient extended industri al temperature range in the 208-ball sparse mbga package only . please contact your local authorized adi sales representati ve for ordering information. part number temperature range (ambient) speed grade (max) operating voltage (nominal) adsp-bf534bbc-4a1 C40oc to 85oc 400 mhz 1.2 v internal, 2.5 v or 3.3 v i/o adsp-bf534bbcz-4a1 C40oc to 85oc 400 mhz 1.2 v internal, 2.5 v or 3.3 v i/o ADSP-BF534BBCZ-4B1 C40oc to 85oc 400 mhz 1.2 v internal, 2.5 v or 3.3 v i/o adsp-bf534bbc-5a1 C40oc to 85oc 500 mhz 1.26 v internal, 2.5 v or 3.3 v i/o adsp-bf534bbcz-5a1 C40oc to 85oc 500 mhz 1.26 v internal, 2.5 v or 3.3 v i/o adsp-bf534bbcz-5b1 C40oc to 85oc 500 mhz 1.26 v internal, 2.5 v or 3.3 v i/o
rev. pre | page 60 of 60 | july 2005 adsp-bf534 preliminary technical data ? 2005 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners.

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